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Power gating technique for reducing leakage power in digital asynchronous GasP circuits

机译:降低数字异步GasP电路泄漏功率的功率门控技术

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There are multiple methods to reduce power consumption of digital circuits one of them is power gating. This paper introduces a new Power Gating technique for the GasP family of asynchronous circuits to achieve power savings. Large amount of power utilization in digital circuits is due to leakage current, as sub threshold conduction, junction leakage, and tunneling leakage through gate oxide. As per result from experiment, it is found that power gating is the most effective method to reduce sub threshold leakage. In power, gating there is a PMOS, a NMOS transistor is used to provide virtual power supply to block which is known as Virtual VDD and Virtual GND. NMOS, and PMOS transistor is known as sleep transistors. The power control logic turns on the power in anticipation of the receiving signal. The power control logic turns off the power when the circuit block is idle because either it is empty or pipeline is obstructed. GasP circuit make possible power gating is used in each stage. A latch is used in this article for storing the data coming from previous stage. This latch is power efficient because it drives only when necessary. It preserve its output and permits power gating.
机译:有多种降低数字电路功耗的方法,其中之一就是功率门控。本文介绍了一种用于GasP系列异步电路的新功率门控技术,以实现节能。数字电路中的大量功率使用归因于泄漏电流,例如低于阈值的导通,结泄漏和通过栅极氧化物的隧穿泄漏。根据实验结果,发现功率门控是减少亚阈值泄漏的最有效方法。在电源中,有一个PMOS门控,一个NMOS晶体管用于为模块提供虚拟电源,称为虚拟VDD和虚拟GND。 NMOS和PMOS晶体管被称为睡眠晶体管。功率控制逻辑在预期接收信号时打开电源。当电路块空闲时,电源控制逻辑将关闭电源,这是因为电路块为空或管道受阻。 GasP电路可在每个阶段使用电源门控。本文中使用了一个锁存器来存储来自上一阶段的数据。该锁存器省电,因为它仅在必要时才驱动。它保留其输出并允许电源门控。

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