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Exploring Parallelism in MiBench with Loop and Procedure Level Speculation

机译:通过循环和过程级推测探索MiBench中的并行性

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The effective utilization of the abundant computation resources provided by Chip Multi-Processor (CMP? to speedup serial programs, has been received with various methods by many researchers making it a major research hotspot. However, embedded applications have not yet been thoroughly examined in thread level speculation (TLS), as compared to how researchers have focused and addressed other areas. In this paper, we propose kernel data structures of loop and procedure level speculation to accelerate serial programs. To verify the hypothesis, we choose some applications from Mibench, discuss codes and the impact of TLS technology features on the speedup such as coverage parallelism, dependence features, threads size, and core numbers. The experiment results prove that firstly, speculative thread level parallelism is better than instruction level parallel technology. Secondly, the best dijkstra application has a result 13.3x speedup in loop level speculation and a 29.7x speedup in procedure level. Thirdly, in the field of embedded applications, the TLS technology can effectively utilize resources of 4 to 8 core computing and procedure level speculation is better than loop level speculation.
机译:许多研究人员已通过各种方法有效利用了芯片多处理器(CMP)提供的大量计算资源来加速串行程序,这使其成为一个主要的研究热点,但是,嵌入式应用程序尚未在线程中进行全面研究。层级推测(TLS),与研究人员专注于其他领域的方式相比,本文提出了循环级和过程级推测的内核数据结构以加速串行程序。为验证这一假设,我们从Mibench中选择了一些应用程序,讨论了代码以及TLS技术特性对覆盖并行性,依赖特性,线程大小和核数等对加速的影响,实验结果证明,推测性线程级并行性优于指令级并行技术。 dijkstra应用程序的循环级推测速度提高了13.3倍,而procedu的速度提高了29.7倍重新级别。第三,在嵌入式应用领域,TLS技术可以有效地利用4到8个核心计算资源,并且过程级别的推测要好于循环级别的推测。

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