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首页> 外文会议>2018 Second International Conference on Electronics, Communication and Aerospace Technology >Design and Simulation of 16×16 bit Iterative Logarithmic Multiplier for Accurate Results
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Design and Simulation of 16×16 bit Iterative Logarithmic Multiplier for Accurate Results

机译：精确结果的16×16位迭代对数乘法器的设计与仿真

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摘要

Multiplication is a basic arithmetic operation. Multiplication operations such as Fast Fourier Transforms, Multiplication and accumulation units, Convolution are some of the computation-intensive arithmetic functions often encountered in Digital Signal Processing applications. Usually, Logarithm based multipliers are used in these cases which introduce certain errors. These errors are approximated by various methods. In this paper a simple architecture of a 16×16 logarithm based multiplier is proposed which uses simple combinational and sequential circuits to obtain an exact product. The multiplier has an arbitrary execution time with the maximum execution time being 15 clock cycles and mean being 7.5 clock cycles. This architecture is designed and simulated in ‘ModeISim’ simulation tool.
机译：乘法是基本的算术运算。诸如快速傅立叶变换，乘法和累加单元，卷积之类的乘法运算是数字信号处理应用程序中经常遇到的一些计算密集型算术函数。通常，在这些情况下使用基于对数的乘法器，这会带来某些误差。这些误差可以通过各种方法来近似。本文提出了一种基于16×16对数的乘法器的简单架构，该架构使用简单的组合电路和顺序电路来获得精确乘积。乘法器具有任意执行时间，最大执行时间为15个时钟周期，平均为7.5个时钟周期。该架构是在“ ModeISim”仿真工具中设计和仿真的。

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