A Methodology to Verify Digital IP's within Mixed-Signal Systems

机译：验证混合信号系统中数字IP的方法

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This paper describes a methodology to improve the quality of verification and an approach to dimension the arithmetic of register transfer level (RTL) model of the digital part of the mixed-signal system. This includes the refinement of the high level model of the system and generation of a MATLAB fixed-point model and test-bench for MATLAB-HDL cosimulation. Additionally an approach for the dimensioning of an adaptive equalizer in frequency domain is discussed. The proposed methodology and results of analysis are applied to verify 10BASE-T/100BASE-TX Ethernet PHY IP.

机译：本文介绍了一种提高验证质量的方法，以及一种确定混合信号系统数字部分的寄存器传输级（RTL）模型的算法尺寸的方法。这包括完善系统的高级模型，以及生成用于MATLAB-HDL协同仿真的MATLAB定点模型和测试平台。另外，讨论了一种在频域中确定自适应均衡器尺寸的方法。所提出的方法和分析结果可用于验证10BASE-T / 100BASE-TX以太网PHY IP。

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来源
《21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems》|2018年|162-165|共4页
会议地点 Budapest(HU)
作者
Navaneetha Channiganathota Manjappa; Anselm Breitenreiter; Markus Ulbricht; Milos Krstic;
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正文语种 eng
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关键词
Mathematical model; Quantization (signal); Matlab; Adaptation models; Hardware design languages; Receivers; Servers;

机译：数学模型；量化（信号）； Matlab；适应模型；硬件设计语言；接收器；服务器；;

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1. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J] . Badaroglu M., van Heijningen M., Gravot V., IEEE Journal of Solid-State Circuits . 2002,第11期

机译：具有同步数字电路的CMOS混合信号IC中降低基板噪声的方法和实验验证
2. Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits [J] . Badaroglu M., van Heijningen M., Gravot V., IEEE Journal of Solid-State Circuits . 2002,第11期

机译：具有同步数字电路的CMOS混合信号IC中降低基板噪声的方法和实验验证
3. Leading-Edge Computer Aided Design Solutions for Advanced Digital and Mixed-Signal Systems-on-Chips [J] . Singh R., Cohn J. M. Proceedings of the IEEE . 2007,第3期

机译：先进的计算机辅助设计芯片解决方案，用于高级数字和混合信号片上系统
4. A Methodology to Verify Digital IP's within Mixed-Signal Systems [C] . Navaneetha Channiganathota Manjappa, Anselm Breitenreiter, Markus Ulbricht, IEEE International Symposium on Design and Diagnostics of Electronic Circuits Systems . 2018

机译：一种验证混合信号系统内数字IP的方法
5. Built-in self-test methodologies for concurrent testing of analog/mixed-signal systems-on-chip. [D] . Kulovic, Kemal. 2012

机译：内置自测方法，可同时测试片上模拟/混合信号系统。
6. Industrial methodology for process verification in research (IMPROVER): toward systems biology verification [O] . Pablo Meyer, Julia Hoeng, J. Jeremy Rice, -1

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7. 16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits [O] . Mustafa Badaroglu, Marc Van Heijningen, Vincent Gravot, 2008

机译：16.6具有同步数字电路的CmOs混合信号集成电路中降低基板噪声的方法和实验验证

A Methodology to Verify Digital IP's within Mixed-Signal Systems

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