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首页> 外文会议>9th International Autumn Meeting on Gettering and Defect Engineering in Semiconductor Technology (GADEST 2001), Sep 30-Oct 3, 2001, S. Tecla, Italy >Influence of Ge Content on Electrical Properties: Sheet Resistance and Hall Mobility in Ion Beam Synthesized Si_(1-x)Ge_x Alloy
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Influence of Ge Content on Electrical Properties: Sheet Resistance and Hall Mobility in Ion Beam Synthesized Si_(1-x)Ge_x Alloy

机译：Ge含量对电性能的影响：离子束合成Si_（1-x）Ge_x合金的薄层电阻和霍尔迁移率

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摘要

We investigated the influence of the Ge content on sheet resistance and Hall mobility of ion beam synthesised Si_(1-x)Ge_x alloy (x=0 to 15%) doped with boron (x = 1e20 B/cm~3). The experiment was conducted using Si and Silicon On Insulator substrates. Prior to annealing for solid phase epitaxial growth and dopant activation at 1050℃, some material was also post-amorphised by Si~+ implantation using 5el5 Si~+cm~2 at 250keV. Room temperature sheet resistance and Hall mobility were measured using the Van der Pauw method. Under the annealing conditions performed, we observed an increase in sheet resistance and a decrease in Hall mobility with increasing Ge content for both silicon and SOI material. However, the hole drift mobility, estimated from Hall mobility, increased with Ge content with a value of ≈ 104 cm~2/V-s in layers with a peak Ge content of 15 at%. Possible interpretations of these results are discussed with reference to the boron chemical profiles from SIMS analysis. The re-grown material quality was investigated using XTEM observations from selected samples.
机译：我们研究了锗含量对掺硼（x = 1e20 B / cm〜3）的离子束合成Si_（1-x）Ge_x合金（x = 0至15％）的薄层电阻和霍尔迁移率的影响。使用绝缘体上的硅和硅衬底进行了实验。在1050℃进行固相外延生长和掺杂剂活化退火之前，还通过在250keV下使用5el5 Si〜+ cm〜2进行Si〜+注入使某些材料后非晶化。室温薄层电阻和霍尔迁移率是使用Van der Pauw方法测量的。在所执行的退火条件下，我们观察到硅和SOI材料的薄膜电阻均随Ge含量的增加而增加，霍尔迁移率也随之降低。然而，根据霍尔迁移率估算的空穴漂移迁移率随Ge含量的增加而增加，其峰值Ge含量为15 at％的层中的≈104 cm〜2 / V-s。参照SIMS分析中的硼化学曲线讨论了这些结果的可能解释。使用从选定样品中获得的XTEM观察值对再生的材料质量进行了研究。

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