VLIW processor architecture adapted to FPAs

机译：适用于FPA的VLIW处理器架构

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Abstract: A new processor architecture intended to be integrated with a CMOS image sensor is presented. This association allows to design an intelligent camera that can perform on-chip image processing tasks. The processor is based on a VLIW architecture with a reduced instruction bus, able to execute multiple instructions in a parallel without any loss of performance. In addition, no more instruction cache is required, decreasing in this way the hardware complexity. !7

机译：摘要：提出了一种旨在与CMOS图像传感器集成的新处理器架构。这种关联允许设计一个可以执行片上图像处理任务的智能相机。该处理器基于具有减少的指令总线的VLIW架构，能够并行执行多个指令而不会降低性能。另外，不需要更多的指令高速缓存，以这种方式降低了硬件复杂度。！7

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来源
《Advanced Focal Plane Arrays and Electronic Cameras II》|1998年|p.128-132|共5页
会议地点 Zurich(CH)
作者
Laurent Petit; Univ. Catholique de Louvain; Louvain la Neuve; Belgium; Jean-Didier Legat; Univ. Catholique de Louvain; Louvain-la-Neuve; Belgium.;
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正文语种 eng
中图分类一般工业技术;
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1. mAgic-FPU and MADE: A customizable VLIW core and the modular VLIW processor architecture description environment [J] . Pier S. Paolucci, Philippe Kajfasz, Philippe Bonnot, Computer physics communications . 2001,第1期

机译：mAgic-FPU和MADE：可定制的VLIW内核和模块化VLIW处理器体系结构描述环境
2. Merging VLIW and vector processing techniques for a simple, high-performance processor architecture [J] . Soliman Mostafa I. Microelectronics journal . 2015,第7期

机译：融合VLIW和矢量处理技术，形成简单的高性能处理器体系结构
3. Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture [J] . Cheng-Yu Lee, Min-Chin Hung, Rong-Guey Chang Concurrency and computation: practice and experience . 2014,第1期

机译：具有共享寄存器架构的VLIW统一精简指令集计算机/数字信号处理器处理器的指令调度和转换
4. VLIW processor architecture adapted to FPAs [C] . Laurent Petit, Jean-Didier Legat Conference on advanced focal plane arrays and electronic cameras . 1998

机译：VLIW处理器架构适用于FPAS
5. Complementary compiler and architecture features for embedded VLIW processors. [D] . Stotzer, Eric J. 2010

机译：嵌入式VLIW处理器的互补编译器和体系结构功能。
6. Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures [O] . Haijing Tang, Xu Yang, Siye Wang, 2013

机译：连接寄存器文件的集群式VLIW架构的优化指令调度和寄存器分配
7. System of Combined Specialized Test Generators for the New Generation of VLIW DSP Processors with Elcore50 Architecture [O] . A.V. Garashchenko, A.V. Nikolaev, F.M. Putrya, 2019

机译：具有ELCORE50架构的新一代VLIW DSP处理器组合专业测试发生器系统

VLIW processor architecture adapted to FPAs

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