Abstract: Lodging a digital processing element (PE) in each pixel of a focal plane array is the challenge to be taken up to get programmable artificial retinas (PAR) that can be used in a large variety of applications. Using semi-static memory and communication structures together with charge sharing based computing circuitry, we elaborate a PE architecture of which the computational power versus area ratio improves over all previously known attempts. A key feature is the ability of neighbor PEs to be gathered into clusters allowing to get virtual memory through multigranularity computation. A 128 $MUL 128 PAR, called PVLSAR 2.2, has been fabricated accordingly with 5 binary registers per PE. Each PE fits within a 15k$lambda$+2$/ silicon area$LR@. !14
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