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A VLSI Chip for Computing the Medial Axis Transform of an Image

机译:用于计算图像中轴变换的VLSI芯片

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In this paper, we describe a new special purpose VLSI architecture for computing the medial axis transform of an image. The architecture is systolic and is based on an algorithm that achieves a high degree of parallelism. The proposed algorithm computes the skeleton of multiple objects in an image in linear time by making 2 scans over the 4-distance transform of the image. The algorithm is mapped onto a linear systolic array of simple processing elements (PEs) and for an NxN image, the architecture requires N PE's. The entire array can be realized in a single VLSI chip. The proposed hardware can perform thinning on a 512×512 image in 2.59 msec and on a 256×256 image in 0.327 msec. A prototype CMOS VLSI chip implementing the proposed architecture has been designed and verified.
机译:在本文中,我们描述了一种新的专用VLSI架构,用于计算图像的中轴变换。该体系结构是收缩的,并且基于实现高度并行性的算法。该算法通过对图像的4距离变换进行2次扫描,从而在线性时间内计算出图像中多个对象的骨架。该算法被映射到简单处理元素(PE)的线性脉动阵列上,对于NxN图像,该体系结构需要N PE。整个阵列可以在单个VLSI芯片中实现。所提出的硬件可以在2.59毫秒内对512×512图像和在0.327毫秒内对256×256图像执行间隔剔除。已设计并验证了实现所建议架构的CMOS VLSI原型芯片。

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