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首页> 外文会议>Conference on Design for Manufacturability through Design-Process Integration; 20080128-29; San Jose,CA(US) >Device Performance-based OPC for Optimal Circuit Performance and Mask Cost Reduction
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Device Performance-based OPC for Optimal Circuit Performance and Mask Cost Reduction

机译：基于器件性能的OPC可实现最佳电路性能并降低掩模成本

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摘要

During the Design-to-Manufacturing tape out flow, Optical Proximity Correction (OPC) is commonly adopted to correct the systematic proximity-effects-caused patterning distortions in order to minimize the across-gate and across-chip linewidth variation. With the continued scaling of gate length, the OPC correction scheme inevitably becomes more aggressive nowadays; increasing the mask complexity and cost proportionally. This could partly be attributed to the purely geometry-based OPC algorithm which tries to match every edge in the layout, without considering its actual impact on circuit performance. Therefore, possibility exists for over-corrected OPC mask that bring slight improvement in circuit performance at the expense of disproportionate higher cost. To simplify the mask design, we present a device performance-based OPC (DPB-OPC) algorithm to generate the mask based on the performance matching criteria rather than the geometrical pattern matching criteria. Drive current (Ion) and leakage current (Ioff) of transistor are chosen to be the performance indexes in this DPB-OPC flow. When compared to the conventional OPC approaches, our proposed approach results in simpler mask that achieves closer circuit performance.
机译：在从设计到制造的磁带流出过程中，通常采用光学邻近校正（OPC）来校正系统的邻近效应引起的图案变形，以最大程度地减少跨栅和跨芯片的线宽变化。随着栅极长度的不断扩展，当今的OPC校正方案不可避免地变得更加激进。按比例增加掩模的复杂性和成本。这可能部分归因于纯粹基于几何的OPC算法，该算法尝试匹配布局中的每个边缘，而不考虑其对电路性能的实际影响。因此，存在过度校正的OPC掩模的可能性，其以不成比例的较高成本为代价带来电路性能的轻微改善。为了简化掩模设计，我们提出了一种基于设备性能的OPC（DPB-OPC）算法，该算法基于性能匹配标准而不是几何图案匹配标准来生成掩模。选择晶体管的驱动电流（Ion）和泄漏电流（Ioff）作为该DPB-OPC流程中的性能指标。与传统的OPC方法相比，我们提出的方法可简化掩膜，实现更近的电路性能。

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