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首页> 外文会议>Conference on Design for Manufacturability through Design-Process Integration; 20080128-29; San Jose,CA(US) >A Routing Clean-Up Methodology for Improvement of Defect and Lithography Related Yield
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A Routing Clean-Up Methodology for Improvement of Defect and Lithography Related Yield

机译：用于改善缺陷和光刻相关产量的工艺路线清理方法

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摘要

Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs. Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.
机译：粒子引起的缺陷仍然是半导体制造中良率损失的主要来源之一。另外，形状的光学畸变在现代技术中不可忽视，并且需要增加设计工作量，以避免产量损失并使制造成本最小化。尽管自动路由工具的供应商越来越多地解决这些问题，但即使在由DfM感知的路由器生产的布局中，我们仍然看到了巨大的改进潜力。我们提出了布线后清理步骤，以解决布线层中与缺陷和光刻相关的良率损失。与“查找并修复”方法相反，此方法基于形状简化和标准化的一般概念“通过构造”创建了光刻友好的布局。

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