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首页> 外文会议>Conference on Emerging Lithographic Technologies Ⅴ Feb 27-Mar 1, 2001, Santa Clara, USA >Application of Advanced 100-kV EB Writer (EB-X3) for 100-nm Node X-ray Mask Fabrication
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Application of Advanced 100-kV EB Writer (EB-X3) for 100-nm Node X-ray Mask Fabrication

机译：先进的100kV EB写入器（EB-X3）在100nm节点X射线掩模制造中的应用

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Most important issues in a precise X-ray mask fabrication are the mask materials and EB writing to achieve good accuracy in critical dimension (CD) control and image placement (IP). However, 1-to-l X-ray mask is required severe accuracy in comparison with photo reticles. The following discussions focus on how to realize the precise IP accuracy. We installed and evaluated 100-Kv electron-beam (EB) mask writer (EB-X3), and developed the writing process on a thin membrane. Key factors in accurate EB mask writing include not only EB positioning accuracy but also mask distortions caused by mask holding and the temperature change of the mask and a mask holder. This paper presents mask distortion characteristics due to the holding, temperature change, and then, good results of mask accuracy of 4-Gb dynamic random access memory (DRAM) test patterns (gate and contact layers) and 90 nm SRAM test patterns. In addition, we employed the advanced PAT method with 4-multi-pass writing that adequately compensates the process-induced mask distortion and the beam drift. These improvements resulted in IP accuracy of better than 10 nm (3σ), 100 nm CD uniformity within 8 nm (mean shift +- 3σ) and the overlay accuracy within 10 nm for 4-Gb gate and contact layers with a 24 mm X 24 mm area on the X-ray membrane mask. These results demonstrate that we can actually fabricate precise X-ray membrane masks that meet our final target of IP accuracy corresponding to the 100 nm technology node.
机译：精确的X射线掩模制造中最重要的问题是掩模材料和EB写入，以在临界尺寸（CD）控制和图像放置（IP）中获得良好的精度。然而，与光罩相比，一对一的X射线光罩要求严格的精度。以下讨论集中于如何实现精确的IP准确性。我们安装并评估了100 Kv电子束（EB）掩模写入器（EB-X3），并开发了在薄膜上的写入过程。精确的EB掩模写入的关键因素不仅包括EB定位精度，还包括由掩模固定以及掩模和掩模支架的温度变化引起的掩模变形。本文介绍了由于保持，温度变化以及随后的4 Gb动态随机存取存储器（DRAM）测试图案（栅极和接触层）和90 nm SRAM测试图案的掩模精度而产生的良好掩模失真特性。此外，我们采用了具有4次多遍写入功能的高级PAT方法，该方法可以充分补偿过程引起的掩模失真和光束漂移。这些改进导致24毫米X 24的4 Gb栅极和接触层的IP精度优于10 nm（3σ），CD均匀性在8 nm以内（平均偏移+-3σ），并且覆盖精度在10 nm以内X射线膜罩上的mm区域。这些结果表明，我们实际上可以制造出满足我们最终IP精度目标（对应于100 nm技术节点）的精确X射线膜掩模。

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