A Laboratory on a Chip for Test Engineering Education

机译：测试工程教育的芯片实验室

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This paper will discuss the concept design and potential utilisation of a novel architecture reconfigurable integrated circuit (IC) aimed at supporting the teaching of Integrated Circuit test engineering concepts. The objective is to provide a single configurable device that allows for the downloading of specific circuit designs, along with specific target circuit faults into a digital configurable array. As such, it can provide the potential to be a highly flexible and interactive device for IC hardware test strategy development, acting as a single IC based hardware laboratory, and may complement a corresponding fault simulation study. This paper will discuss the design of a demonstrator version of the array whose functionality may be extended. The potential users will be persons investigating IC test concepts and techniques.

机译：本文将讨论旨在支持集成电路测试工程概念教学的新型体系结构可重配置集成电路（IC）的概念设计和潜在利用。目的是提供单个可配置设备，该设备允许将特定电路设计以及特定目标电路故障下载到数字可配置阵列中。这样，它有可能成为IC硬件测试策略开发的高度灵活和交互式的设备，充当基于单个IC的硬件实验室，并且可以补充相应的故障仿真研究。本文将讨论阵列的演示器版本的设计，其功能可能会得到扩展。潜在的用户将是研究IC测试概念和技术的人员。

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来源
《Conference on Sensors and Their Applications; 20030902-20030904; Limerick; IE》|2003年|P.45-52|共8页
会议地点 Limerick(IE)
作者
I A Grout; J Walsh; T OShea; M Canavan;
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Department of Electronic and Computer Engineering, University of Limerick, Ireland;

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原文格式 PDF
正文语种 eng
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A Laboratory on a Chip for Test Engineering Education

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