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OPC on Real World Circuitry

机译：OPC在现实世界中的电路

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In the face of Moore's Law, the lithographic community is finding increasing pressure to do more with less. More, in the sense that lithographers are expected to use an exposure wavelength "lambda" that is shrinking at a slower rate than the critical dimensions (CDs) of devices. This has resulted in the introduction of complicated Resolution Enhancement Technology (RET) schemes. Less, in the sense that the competitive marketplace has resulted in shortened development cycles. These shortened development times mean that lithography and RET teams are often expected to demonstrate "first pass success" with increasing complex lithographic solutions. Unfortunately, first silicon on product prototypes may reveal deficiencies in an OPC infrastructure which had been developed using only research and development (R&D) testdie. The primary cause of these deficiencies is that the development and test-structure layouts frequently lack the 2-D complexity of real circuitry. OPC models and lithography R&D traditionally compensate well for failures and marginal sites on the simple patterns of R&D testdie. The more complex geometries of real layouts frequently present new challenges. Here, we describe a program initiated at TI to add a complex pattern to the very first test reticle generated for a new technology node. This pattern is auto-generated and includes a random combination of representative circuits at the design rule for that node. OPC is applied to the pattern almost immediately after layout. The distribution of printed features and marginal sites can then be identified early using simulation. Scanning Electron Microscope (SEM) images of resist and post-etch features can further identify sites requiring changes once reticles are received. We have shown that this early OPC R&D on complex geometries can prevent several OPC revision cycles and enable faster volume yield ramp.
机译：面对摩尔定律，光刻界正在发现越来越大的压力，要求事半功倍。从某种意义上说，期望光刻师使用的曝光波长“λ”以比器件的临界尺寸（CD）慢的速率收缩。这导致引入了复杂的分辨率增强技术（RET）方案。从竞争性市场导致缩短的开发周期的意义上讲，它的数量更少。这些缩短的开发时间意味着，随着越来越复杂的光刻解决方案的发展，通常期望光刻和RET团队展示出“首过成功”。不幸的是，产品原型上的第一个硅片可能显示出仅使用研发（R＆D）测试模具开发的OPC基础设施中的缺陷。这些缺陷的主要原因是开发和测试结构布局经常缺乏实际电路的二维复杂性。传统上，OPC模型和光刻研发可以在简单的研发测试模具上很好地补偿故障和边缘部位。实际布局的更复杂几何形状经常带来新的挑战。在这里，我们描述了TI发起的一个程序，该程序将为新技术节点生成的第一个测试标线添加复杂的模式。此模式是自动生成的，并且在该节点的设计规则处包括代表电路的随机组合。 OPC几乎在布局后立即应用于图案。然后可以使用模拟及早识别出印刷特征和边缘部位的分布。抗蚀剂和刻蚀后特征的扫描电子显微镜（SEM）图像可以进一步识别出收到标线后需要更改的位置。我们已经表明，针对复杂几何形状的OPC的这种早期研发可以防止多个OPC修订周期，并可以更快地提高产量。

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