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Performance-Impact Limited Area Fill Synthesis

机译：性能影响有限区域填充合成

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摘要

Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local layout density. To improve manu-facturability and performance predictability, area fill features are inserted into the layout to improve uniformity with respect to density criteria. However, the performance impact of area fill insertion is not considered by any fill method in the literature. In this paper, we first review and develop estimates for capacitance and timing overhead of area fill insertion. We then give the first formulation of the Performance Impact Limited Fill (PIL-Fill) problem, and describe three practical solution approaches based on Integer Linear Programming (ILP-Ⅰ and ILP-Ⅱ) and the Greedy method. We test our methods on two layout testcases obtained from industry. Compared with the normal fill method, our ILP-Ⅱ method achieves between 25% and 90% reduction in terms of total weighted edge delay (roughly, a measure of sum of node slacks) impact, while maintaining identical quality of the layout density control.
机译：根据局部布局密度的不同，超深亚微米VLSI中的化学机械平面化（CMP）和其他制造步骤会对器件和互连功能产生不同的影响。为了提高可制造性和性能可预测性，将面积填充特征插入布局中以提高相对于密度标准的均匀性。但是，文献中没有任何填充方法考虑区域填充插入对性能的影响。在本文中，我们首先回顾和发展对电容和面积填充插入时序开销的估计。然后，我们给出了性能影响受限填充（PIL-Fill）问题的第一个公式，并描述了基于整数线性规划（ILP-Ⅰ和ILP-Ⅱ）和贪婪方法的三种实际解决方法。我们在两个从行业获得的布局测试用例上测试了我们的方法。与常规填充方法相比，我们的ILP-Ⅱ方法在总加权边缘延迟（大致是节点松弛之和的一种度量）影响方面可减少25％至90％，同时保持相同的布局密度控制质量。

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