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From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors

机译：从折线到晶体管：为非矩形晶体管建立BSIM模型

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Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.
机译：当今先进工艺中的非矩形晶体管在制造和设计之间提出了一个潜在的问题，因为当今的紧凑型晶体管模型只有一个长度和一个宽度参数来描述栅极尺寸。晶体管模型是制造与设计之间的关键环节，随着转角圆角以及其他2D邻近效应变得更加明显，需要考虑跨栅极CD的变化。这是一个复杂的问题，因为阈值电压和泄漏电流与栅极长度具有非常复杂的非线性关系。已经尝试将非矩形栅极建模为并行的晶体管，但是这种方法由于缺乏用于“切片晶体管”的精确模型而受到困扰，这可能需要新的电路模拟器和新的复杂方程组。本文将提出一种新方法，该方法可以用等效的矩形晶体管近似非矩形晶体管，因此不需要新的晶体管模型或电路模拟器的重大更改。有效的长度提取包括将非矩形晶体管分成矩形切片，然后根据HSPICE中的模拟切片电流进行加权平均。只要将不同的有效长度用于延迟和静态功率分析，仿真结果就会显示等效矩形晶体管的行为与非矩形晶体管相同。

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