首页> 外国专利> THIN FILM TRANSISTOR ARRAY SUBSTRATE, LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR

THIN FILM TRANSISTOR ARRAY SUBSTRATE, LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING LOW TEMPERATURE POLY-SILICON THIN FILM TRANSISTOR

机译:薄膜晶体管阵列基板,低温多晶硅薄膜晶体管以及制造低温多晶硅薄膜晶体管的方法

摘要

The present disclosure provides a low temperature poly-silicon thin film transistor. The low temperature poly-silicon thin film transistor includes a substrate, a poly-silicon layer formed at a surface of the substrate, an insulating layer, a gate electrode, a first control electrode, a second control electrode, a source electrode, and a drain electrode. The insulating layer covers the poly-silicon layer. A gap between the first control electrode and the gate electrode and a gap between the second control electrode and the gate electrode correspond to offset regions of the poly-silicon layer. Two heavily doped regions formed at the poly-silicon layer are respectively located besides the first control electrode and the second control electrode away from the offset regions. The source electrode and the drain electrode are respectively formed at the heavily doped regions.
机译:本公开提供了一种低温多晶硅薄膜晶体管。低温多晶硅薄膜晶体管包括衬底,形成在衬底表面上的多晶硅层,绝缘层,栅电极,第一控制电极,第二控制电极,源电极和衬底。漏电极。绝缘层覆盖多晶硅层。第一控制电极和栅电极之间的间隙以及第二控制电极和栅电极之间的间隙对应于多晶硅层的偏移区域。形成在多晶硅层处的两个重掺杂区域分别远离第一控制电极和第二控制电极而位于远离偏移区域的位置。源电极和漏电极分别形成在重掺杂区。

著录项

  • 公开/公告号US2019319134A1

    专利类型

  • 公开/公告日2019-10-17

    原文格式PDF

  • 申请/专利权人 SHENZHEN ROYOLE TECHNOLOGIES CO. LTD.;

    申请/专利号US201616462306

  • 发明设计人 XIAOMING CHEN;

    申请日2016-12-24

  • 分类号H01L29/786;H01L29/66;

  • 国家 US

  • 入库时间 2022-08-21 12:12:28

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