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首页> 外文会议>Device packaging 2010 >Improved Heat Dissipation and Optical Performance of High-power LED Packaging with Sintered Nanosilver Die-attach Material
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Improved Heat Dissipation and Optical Performance of High-power LED Packaging with Sintered Nanosilver Die-attach Material

机译：烧结纳米银贴片材料改善了大功率LED封装的散热和光学性能

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摘要

Heat removal in packaged high-power light-emitting diode (LED) chips is critical to device performancernand reliability. Thermal performance of LEDs is important in that lowered junction temperatures extend thernLED’s lifetime at a given photometric flux (brightness). Optionally, lower thermal resistance can enable increasedrnbrightness operation without exceeding the maximum allowable Tj for a given lifetime. A significant portion of thernjunction-to-case thermal resistance comes from the joint between chip and substrate, or the die-attach layer. Inrnthis study, we evaluated three different types of leading die-attach materials; silver epoxy, lead-free solder, and anrnemerging nanosilver paste. Each of the three was processed via their respective physical and chemicalrnmechanisms: epoxy curing by cross-linking of polymer molecules; intermetalic soldering by reflow andrnsolidification; and nanosilver sintering by solid-state atomic diffusion. High-power LED chips with a range ofrnchip areas from 3.9 mm2 to 9.0 mm2 were attached by the three types of materials onto metalized aluminum nitridernsubstrates, wire-bonded, and then tested in an electro-optical setup. The junction-to-heatsink thermal resistance ofrneach LED assembly was determined by the wavelength shift methodology. We found that the average thermalrnresistance in the chips attached by the nanosilver paste was the lowest, and it was highest from the chips attached byrnthe silver epoxy. For the 3. 9 mm2 die, the difference was about 0.6oC/W, while the difference between the sinteredrnand soldered was about 0.3oC/W. The lower thermal resistance in the sintered joints is expected to significantlyrnimprove the photometric flux from the device. Simple calculations, excluding high current efficiency droop, predictrnthat the brightness improvement could be as high as 50% for the 3.9 mm2 chip. The samples will be functionallyrntested at high current, in both steady-state and pulsed operation, to determine brightness improvements, includingrnthe impact of droop. Nanosilver die-attach on a range of chip sizes up to 12 mm2 are also considered andrndiscussed.
机译：封装的大功率发光二极管（LED）芯片中的散热对于设备性能和可靠性至关重要。 LED的热性能很重要，因为在给定的光通量（亮度）下，降低的结温可以延长LED的使用寿命。可选地，较低的热阻可以在不超过给定寿命的最大允许Tj的情况下提高亮度操作。外壳到外壳的热阻的很大一部分来自芯片与基板之间的接合处，或芯片附着层。在这项研究中，我们评估了三种不同类型的领先芯片连接材料。环氧银，无铅焊料和纳米银浆。三种方法分别通过各自的物理和化学机理进行处理：通过聚合物分子的交联进行环氧固化；通过回流和凝固进行金属间焊接；固态原子扩散进行纳米银烧结。通过三种类型的材料将面积从3.9 mm2到9.0 mm2的高功率LED芯片附着到金属化的氮化铝衬底上，进行引线键合，然后在电光装置中进行测试。每个LED组件的结至散热器的热阻通过波长偏移方法确定。我们发现，纳米银浆粘贴的芯片的平均热阻最低，而环氧银粘贴的芯片的平均热阻最高。对于3. 9 mm2的芯片，差异约为0.6oC / W，而烧结和焊接之间的差异约为0.3oC / W。烧结接头中较低的热阻有望显着改善来自设备的光度通量。通过简单的计算（不包括高电流效率下降），可以预测3.9 mm2芯片的亮度提高可能高达50％。样品将在稳态和脉冲操作下在高电流下进行功能测试，以确定亮度的改善，包括下垂的影响。还考虑并讨论了在高达12 mm2的一系列芯片尺寸上进行纳米银管芯贴装的问题。

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  • 来源
    《Device packaging 2010》|2010年|p.1-6|共6页
  • 会议地点 Scottsdale/Fountain Hills AZ(US)
  • 作者

    Paul Panaccione; Tao Wang; Xu Chen; Susan Luo; Guo-Quan Lu;

  • 作者单位

    Luminus Devices Inc., 1100 Technology Park Dr., Billerica, MA 01821 ppanaccione@luminus.com;

    rnDept. of MSE, Virginia Tech, 213 Holden Hall, Blacksburg, VA 24061 School of Chemical Engineering, Tianjin Univ., Tianjin, China;

    School of Chemical Engineering, Tianjin Univ., Tianjin, China;

    NBE Technologies, LLC, 2200 Kraft Dr., Suite 1425, Blacksburg, VA 24060;

    Dept. of MSE, Virginia Tech, 213 Holden Hall, Blacksburg, VA 24061;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 制造工艺;
  • 关键词

    nano-silver; die-attach; LED;

    机译：纳米银;;死贴;发光二极管;

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