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Ultrathin 3D ACA FlipChip-in-Flex Technology

机译：超薄3D ACA FlipChip-in-Flex技术

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Die thickness of common, high-volume chip stacks range between 50-100 μm while thinning industry aims towards ultrathinrnchips of 10 μm thickness or even below. For the first time, the required interconnect length between vertically arranged adjacentrnchip layers has therewith reached dimensions, that can be reasonably realized by anisotropic conductive adhesives layers (ACA).rnAccordingly, a three dimensional arrangement by alternate stacking of ultra thin flip chips and interposers using anisotropicrnconductive adhesive bonding technology is within the bounds of possibility, such that the conductive particles are forming thernvertical interconnects between the chip-interposer layers.rnBased upon such assembly concept prototypes have been made within a first laboratory scale feasibility study. In combinationrnwith polyimide thin film interposers, ultrathin low pin count ACA bonded test chips with 4-Point-Kelvin- and Daisy-Chainstructuresrnhave been used to build a 4-layer flip chip stack with a thickness of approximately 170 μm without encapsulation. Firstrnelectrical measurements have shown promising results.rnThe reduction to basically one bonding technology to realize the chip-interposer- and the interposer-interposer connections isrnone of the main benefits with a certain low-cost potential. On the other hand, issues as limited chip/package area ratio, the demandrnfor ultrathin chips with manifold challenges and upcoming detailed electrical characterization of such chip stacks have to bernconsidered. Pros and cons are openly discussed.rnSpecial attraction is provided by applying and combining basically known packaging technologies to obtain an innovative butrnsomehow simple 3D flip chip assembly with certain future application potential.
机译：常见的大批量芯片堆叠的芯片厚度范围在50至100μm之间，而薄板行业的目标是厚度在10μm甚至更低的超薄芯片。第一次，垂直排列的相邻芯片层之间所需的互连长度达到了尺寸，这可以通过各向异性导电胶层（ACA）合理地实现。因此，三维排列是通过交替堆叠超薄倒装芯片和中介层来实现的各向异性的导电粘合剂粘结技术在可能的范围内，使得导电颗粒在芯片插入层之间形成垂直的互连。基于这种组装概念，已经在首次实验室规模的可行性研究中制造了原型。与聚酰亚胺薄膜中介层结合使用时，具有4-Point-Kelvin和Daisy-Chain结构的超薄低引脚数ACA粘合测试芯片已被用于构建厚度约为170μm且无封装的4层倒装芯片堆叠。首次电学测量显示出令人鼓舞的结果。基本上将一种键合技术简化为实现芯片-内插器和内插器-内插器连接的主要好处，同时具有一定的低成本潜力。另一方面，必须考虑以下问题：芯片/封装面积比有限，对超薄芯片的需求面临诸多挑战以及此类芯片堆叠即将进行的详细电学表征。公开和讨论优点和缺点。通过应用和组合基本已知的封装技术来获得具有特殊未来应用潜力的新颖却又简单的3D倒装芯片组件，可以提供特殊的吸引力。

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  • 来源
    《Device packaging 2010》|2010年|p.1-8|共8页
  • 会议地点 Scottsdale/Fountain Hills AZ(US)
  • 作者

    J. Haberland; M. Becker; D. Lütke-Notarp; Ch. Kallmayer; R. Aschenbrenner; H. Reichl;

  • 作者单位

    Berlin Technical University, Research Center Microperipheric Technologies Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

    rnNB Technologies GmbH Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

    rnNB Technologies GmbH Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

    rnFraunhofer Institute Reliability and Microintegration Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

    rnFraunhofer Institute Reliability and Microintegration Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

    rnFraunhofer Institute Reliability and Microintegration Gustav-Meyer-Allee 25, D-13355 Berlin, Germany;

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  • 正文语种 eng
  • 中图分类 制造工艺;
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