首页> 外文会议>ELMAR, 2009. ELMAR '09 >Multiplier circuit with improved linearity using FGMOS transistors
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Multiplier circuit with improved linearity using FGMOS transistors

机译:使用FGMOS晶体管提高线性度的乘法器电路

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An original voltage multiplier circuit will be presented. The circuit is implemented in 0.35um CMOS technology and, in order to improve its frequency response, it is based exclusively on MOS transistors working in saturation region. The utilization of a FGMOST (Floating Gate MOS Transistor) for replacing the classical MOS devices allows obtaining an important reduction of the circuit complexity and, as a result, of the silicon occupied area. The SPICE simulation using the previous mentioned technological parameters confirms the theoretical estimated results, showing an excellent linearity of the new proposed CMOS voltage multiplier circuit.
机译:将展示原始的电压倍增器电路。该电路采用0.35um CMOS技术实现,并且为了改善其频率响应,它完全基于工作在饱和区的MOS晶体管。利用FGMOST(浮栅MOS晶体管)代替传统的MOS器件可以显着降低电路复杂性,从而减少硅的占用面积。使用前面提到的技术参数进行的SPICE仿真证实了理论上的估计结果,显示了新提出的CMOS电压倍增器电路的出色线性度。

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