Improved Design and Characterisation Method for ECL Very High Speed Circuits

机译：ECL超高速电路的改进设计和表征方法

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A procedure to design and characterise high speed bipolar circuits is presented. The design method is improved by using iso base-collector capacitance curves and duty cycles plots in the (Ic, Vce) plane. This new optimisation way gives the optimum electrical parameters for each transistor of a bipolar circuit to reach the best trade-off between the switching speed and the power consumption. Furthermore, input signals time jitter is taken into account during simulations. The measurement method is improved by characterising in time domain each part of the measurement set-up. These improvements have enabled the design and characterisation of InP-DHBT D-type flip-flop and demultiplexer circuits. 40 Gbit/s on wafer measurement are presented.

机译：提出了设计和表征高速双极电路的程序。通过使用（Ic，Vce）平面中的等基极-集电极电容曲线和占空比图来改进设计方法。这种新的优化方法为双极电路的每个晶体管提供了最佳的电参数，以在开关速度和功耗之间达到最佳平衡。此外，在仿真过程中还要考虑输入信号的时间抖动。通过在时域中表征测量设置的每个部分，可以改进测量方法。这些改进使InP-DHBT D型触发器和解复用器电路的设计和特性得以实现。展示了40 Gbit / s的晶圆测量速度。

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来源
《European Microwave Conference vol.2; 20041011-14; Amsterdam(NL)》|2004年|P.909-912|共4页
会议地点 Amsterdam(NL)
作者
A. Kasbari; A. Ouslimani; H. Hafdallah; S. Blayac; A. Konczykowska;
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ENSEA, 6 Avenue du Ponceau, 95014 Cergy, France;

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原文格式 PDF
正文语种 eng
中图分类无线通信;雷达;
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Improved Design and Characterisation Method for ECL Very High Speed Circuits

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