Impact of gate-oxide breakdown on power-gated SRAM

著录项

• 来源
  《IC Design and Technology, 2009. ICICDT '09》|2009年|93-96|共4页
• 会议地点 Austin TX(US);Austin TX(US)
• 作者

  Hao-I Yang; Ching-Te Chuang; Wei Hwang;

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• 作者单位

  Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan;

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• 会议组织
• 原文格式 PDF
• 正文语种
• 中图分类
• 关键词

  SRAM chips; integrated circuit design; integrated circuit noise; semiconductor device breakdown; transistor circuits; cell transistor; column-based header-gated SRAM; drain-to-drain BD; footer-gated SRAM; gate-oxide breakdown; power switch; power-gated SRAM; read static noise margin; write margin; SRAM; power gating technology;

  机译：SRAM芯片;集成电路设计;集成电路噪声;半导体器件击穿;晶体管电路;单元晶体管;基于列的标头栅极SRAM;漏极到漏极BD;页脚栅极SRAM;栅极氧化物击穿;电源开关;电源门控SRAM；读取静态噪声容限；写容限； SRAM；电源门控技术;