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首页> 外文会议>IEEE Joint Conference: International Conference on IC Design and Technology amp; Solid State Systems Symposium >Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling
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Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling

机译：考虑层间耦合的混合TFET-MOSFET单片3D SRAM的探索和评估

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摘要

This paper investigates and evaluates 7T hybrid TFET-MOSFET monolithic 3D SRAM cells considering interlayer coupling for ultra-low voltage operation using TCAD mixed-mode simulations. The planar (2D) 7T hybrid TFET-MOSFET SRAM cell is shown to exhibit equal leakage, better stability and performance compared with the conventional 2D 8T MOSFET SRAM at ultra-low voltage (Vdd ≤ 0.3V). The interlayer coupling, where the front-gate of the bottom tier device alters the back gate bias of the upper tier device, and various stacking and layout arrangements are examined and exploited to improve the stability and performance of monolithic 3D SRAMs. An optimized 3D 7T hybrid SRAM design is shown to exhibit 80% write static noise margin (WSNM) improvement and 24% cell write performance improvement, whereas optimized 3D 8T MOSFET SRAM exhibits 66% WSNM improvement and 33% cell write performance improvement over the planar design. Furthermore, 3D SRAM designs are shown to reduce the SRAM cell area by nearly 40%.
机译：本文研究和评估了考虑使用TCAD混合模式仿真实现超低电压操作的层间耦合的7T混合TFET-MOSFET单片3D SRAM单元。在超低电压（Vdd≤0.3V）下，与传统的2D 8T MOSFET SRAM相比，平面（2D）7T混合TFET-MOSFET SRAM单元显示出相同的泄漏，更好的稳定性和性能。层间耦合（底层器件的前栅极改变了上层器件的后栅极偏置）以及各种堆叠和布局布置均得到了研究和开发，以改善单片3D SRAM的稳定性和性能。经优化的3D 7T混合SRAM设计显示出80％的写入静态噪声裕度（WSNM）改善和24％的单元写入性能改善，而经过优化的3D 8T MOSFET SRAM的WSNM改善了66％，在平面上的性能提高了33％设计。此外，显示3D SRAM设计可将SRAM单元面积减少近40％。

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