An area compact soft error resident circuit for FPGA

机译：FPGA的区域紧凑型软错误驻留电路

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摘要

Due to reaching the nanoscale transistor size, effect of single event upset (SEU) to the memory has become conspicuous. In small device geometries, a single particle strike might affect multiple adjacent cells in a memory array resulting in a multiple bit upset (MBU). Traditional fault tolerance technologies such as triple modular redundancy (TMR) and error correcting code (ECC) occupy the large area and have vulnerability to MBU. In this research, we propose DMR based error correct circuit and employ a combination of proposed circuit and the interleaving technique to mitigate MBU. In addition, we explain soft error simulator developed to calculate bit interleaving distance. The results show that the area of proposed circuit is the smallest when we compare the proposed circuit, ECC based error correct circuit and TMR. Simulation results show that the interleaving distance which can conceal all MBU patterns is 4.

机译：由于达到了纳米级晶体管的尺寸，单事件翻转（SEU）对存储器的影响变得显而易见。在小型设备中，单个粒子撞击可能会影响内存阵列中的多个相邻单元，从而导致多位翻转（MBU）。三层模块化冗余（TMR）和纠错码（ECC）等传统的容错技术占据了很大的面积，并且容易受到MBU的攻击。在这项研究中，我们提出了一种基于DMR的纠错电路，并结合了提出的电路和交织技术来减轻MBU。另外，我们解释了开发用于计算比特交织距离的软错误模拟器。结果表明，与拟议电路，基于ECC的纠错电路和TMR进行比较，拟议电路面积最小。仿真结果表明，可以掩盖所有MBU图样的交织距离为4。

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《IEEE Joint Conference: International Conference on IC Design and Technology amp; Solid State Systems Symposium》|2016年|1-4|共4页
会议地点 Ho Chi Minh City(VN)
作者
Motoki Amagasaki; Yuji Nakamura; Takuya Teraoka; Masahiro Iida; Toshinori Sueyoshi;
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作者单位

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan;

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan;

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan;

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan;

Graduate School of Science and Technology, Kumamoto University, 2-39-1 Kurokami, Chuo-ku, Kumamoto 860-8555, Japan;

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正文语种 eng
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关键词
Field programmable gate arrays; Error correction codes; Random access memory; Tunneling magnetoresistance; Delays; Layout; Single event upsets;

机译：现场可编程门阵列;纠错码;随机存取存储器;隧道磁阻;延迟;布局;单事件扰动;

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专利

1. Domain Crossing Errors: Limitations on Single Device Triple-Modular Redundancy Circuits in Xilinx FPGAs [J] . Quinn H., Morgan K., Graham P., IEEE Transactions on Nuclear Science . 2007,第6期

机译：域交叉错误：Xilinx FPGA中单器件三模块冗余电路的限制
2. Comments on 'A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits' [J] . Kolodziejski J.F., Spiralski L. IEEE Journal of Solid-State Circuits . 1990,第4期

机译：关于“用于研究MOS VLSI数字电路中软错误率的紧凑型热噪声模型”的评论
3. A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits [J] . Layman P.A., Chamberlain S.G. IEEE Journal of Solid-State Circuits . 1989,第1期

机译：用于研究MOS VLSI数字电路中软错误率的紧凑型热噪声模型
4. An area compact soft error resident circuit for FPGA [C] . Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Solid State Systems Symposium . 2016

机译：用于FPGA的区域紧凑型软误差驻留电路
5. Design for soft error tolerance in FPGA-implemented asynchronous circuits [D] . Bai, Yu 2011

机译：FPGA实现的异步电路中的软容错设计
6. Force to Rebalance Control of HRG and Suppression of Its Errors on the Basis of FPGA [O] . Xu Wang, Wenqi Wu, Bing Luo, 2011

机译：基于FPGA的HRG力再平衡控制及其误差抑制
7. ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs [O] . Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, 2014

机译：评估：基于SRAM的FPGA的配置存储器中的软错误模拟器

An area compact soft error resident circuit for FPGA

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