A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process

机译：高通量和低功耗设计，可在65nm SOTB CMOS工艺上进行位图索引

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Massive amounts of data generated from Internet-of-Thing and mobile devices bring a lot of challenges to big data analytics nowadays. In this paper, we propose the high-throughput architecture of a bitmap index creation (BIC) that can greatly accelerate data analytics tasks. BIC is implemented in a low-power 65-nm SOTB CMOS technology to minimize the leakage current in standby mode as well as total power consumption in active mode. By exploiting the hardware parallelism, the indexing throughput surpasses 1.7 times and 2.8 times as high as that of GPU-based and CPU-based designs, respectively. Furthermore, by applying the back bias voltage of -1.5 V, the leakage current significantly reduces approximately 89.2 times, as compared to that at VBB =0.4 V. The power consumption is 4.69 mW, or approximately 27.1 times as low as that of 180-nm bulk CMOS.

机译：物联网和移动设备生成的海量数据为当今的大数据分析带来了许多挑战。在本文中，我们提出了一种位图索引创建（BIC）的高吞吐量体系结构，该体系结构可以大大加速数据分析任务。 BIC采用低功耗65纳米SOTB CMOS技术实现，以最小化待机模式下的泄漏电流以及活动模式下的总功耗。通过利用硬件并行性，索引吞吐量分别超过基于GPU和基于CPU的设计的1.7倍和2.8倍。此外，通过施加-1.5 V的反向偏置电压，与VBB = 0.4 V时相比，泄漏电流显着降低了约89.2倍。功耗为4.69 mW，约为180-V的27.1倍。 nm体CMOS。

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来源
《IEEE Joint Conference: International Conference on IC Design and Technology amp; Solid State Systems Symposium》|2016年|1-4|共4页
会议地点 Ho Chi Minh City(VN)
作者
Xuan-Thuan Nguyen; Hong-Thu Nguyen; Cong-Kha Pham;
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作者单位

The University of Electro-Communications, Tokyo, Japan;

The University of Electro-Communications, Tokyo, Japan;

The University of Electro-Communications, Tokyo, Japan;

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原文格式 PDF
正文语种 eng
中图分类
关键词
CMOS integrated circuits; Clocks; Throughput; Computer aided manufacturing; Leakage currents; Indexing;

机译：CMOS集成电路;时钟;通量;计算机辅助制造;漏电流;分度;

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3. Design of ultra-low power AES encryption cores with silicon demonstration in SOTB CMOS process [J] . V.-P. Hoang, V.-L. Dao, C.-K. Pham Electronics Letters . 2017,第23期

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4. A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process [C] . Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham Solid State Systems Symposium . 2016

机译：在65-NM SOTB CMOS过程中为位图索引的高吞吐量和低功耗设计
5. A hierarchical, automated design flow for low-power, high-throughput digital signal processing IC's. [D] . Davis, William Rhett. 2002

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6. Design of a Low-Power Small-Area AEC-Q100-Compliant SENT Transmitter in Signal Conditioning IC for Automotive Pressure and Temperature Complex Sensors in 180 Nm CMOS Technology [O] . Imran Ali, Behnam Samadpoor Rikhan, Dong-Gyu Kim, 2018

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7. Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology [O] . Masakazu HIOKI, Hanpei KOIKE 2016

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8. A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology [R] . Fang, W. C., Lin, T. H. 1999

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A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process

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