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A hierarchical, automated design flow for low-power, high-throughput digital signal processing IC's.

机译：低功耗，高吞吐量数字信号处理IC的分层自动化设计流程。

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摘要

An automated design flow for direct-mapped digital signal processing systems is presented as a possible solution to the design productivity gap. With current semiconductor processing technologies, there is a growing gap between the number of transistors-per-chip that can be fabricated and the transistors-per-day that can be effectively designed. As a result, the only chips that take advantage of current processing capability are programmable processors with large memories or FPGA's, which are very power and area inefficient. Direct-mapped architectures offer the same throughput while using three to four orders of magnitude less energy and area, but they tend to be avoided because of the immense design effort involved. This work presents an automated flow that allows direct-mapped architectures to be designed with much less effort.; The approach of this flow is similar to the silicon compilers of the previous decade, except that it uses commercial CAD tools. A unified, dataflow-graph-based input description captures the essential decisions: function, signal, circuit, and floorplan decisions. An automated flow much like MAKE invokes CAD tools and carries this description through the different design phases to produce mask layout ready for fabrication and estimates of power and speed. Special attention is given to the preservation of hierarchy throughout the flow to help designers see how the different decisions are related and how to fix problems when particular tools break down. The resulting flow differs significantly from commercial CAD flows, because it is comprised of many small jumps from flow, for instance, never creates a complete register-transfer level (RTL) description for each chip.; The flow is demonstrated on three direct-mapped signal-processing chips ranging in complexity from 300,000 to 600,000 transistors, including an iterative decoder for high-speed magnetic read-channels and a complete TDMA baseband receiver for use in low-power sensor networks. These systems are contrasted with a CDMA receiver designed with an industry-standard flow. An effort is made to quantify the complexity and design effort for each of these projects in order to clarify the benefit of this approach.
机译：提出了直接映射数字信号处理系统的自动化设计流程，作为解决设计生产率差距的一种可能的解决方案。使用当前的半导体处理技术，可以制造的每个芯片的晶体管数量和可以有效设计的每天的晶体管数量之间的差距越来越大。结果，唯一利用当前处理能力的芯片是具有大容量存储器或FPGA的可编程处理器，这在功耗和面积上都非常低效。直接映射架构可提供相同的吞吐量，而能耗和面积却少三到四个数量级，但是由于涉及大量的设计工作，因此倾向于避免直接映射架构。这项工作提出了一种自动化流程，可以以更少的精力设计直接映射的体系结构。除了使用商业CAD工具外，此流程的方法与前十年的硅编译器相似。统一的，基于数据流图的输入描述捕获了基本决策：功能，信号，电路和布局规划决策。类似于MAKE的自动化流程会调用CAD工具，并在不同的设计阶段进行此描述，以生成可用于制造的掩模版图，并估算功率和速度。在整个流程中特别注意保留层次结构，以帮助设计人员了解不同决策之间的关系以及在特定工具出现故障时如何解决问题。最终的流程与商业CAD流程显着不同，因为它包含许多流程上的微小变化，例如，从不为每个芯片创建完整的寄存器传输级别（RTL）描述。在三个直接映射的信号处理芯片上演示了该流程，这些芯片的复杂度从300,000到600,000晶体管不等，包括用于高速磁读取通道的迭代解码器和用于低功率传感器网络的完整TDMA基带接收器。这些系统与按行业标准流程设计的CDMA接收器形成对比。为了阐明这种方法的好处，我们努力量化了每个项目的复杂性和设计工作。

著录项

  • 作者

    Davis, William Rhett.;

  • 作者单位

    University of California, Berkeley.;

  • 授予单位 University of California, Berkeley.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2002
  • 页码 239 p.
  • 总页数 239
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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