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首页> 外文会议>IEEE/ACM Workshop on Fault Tolerance for HPC at eXtreme Scale >Influence of A-Posteriori Subcell Limiting on Fault Frequency in Higher-Order DG Schemes
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Influence of A-Posteriori Subcell Limiting on Fault Frequency in Higher-Order DG Schemes

机译：高阶DG方案中A-Posteriori子单元限制对故障频率的影响

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摘要

Soft error rates are increasing as modern architectures require increasingly small features at low voltages. Due to the large number of components used in HPC architectures, these are particularly vulnerable to soft errors. Hence, when designing applications that run for long time periods on large machines, algorithmic resilience must be taken into account. In this paper we analyse the inherent resiliency of a-posteriori limiting procedures in the context of the explicit ADER DG hyperbolic PDE solver ExaHyPE. The a-posteriori limiter checks element-local high-order DG solutions for physical admissibility, and can thus be expected to also detect hardware-induced errors. Algorithmically, it can be interpreted as element-local checkpointing and restarting of the solver with a more robust finite volume scheme on a fine subgrid. We show that the limiter indeed increases the resilience of the DG algorithm, detecting and correcting particularly those faults which would otherwise lead to a fatal failure.
机译：随着现代架构在低压下要求越来越小的特征，软错误率正在增加。由于HPC体系结构中使用了大量组件，因此这些组件特别容易受到软错误的影响。因此，当设计在大型计算机上长时间运行的应用程序时，必须考虑算法的弹性。在本文中，我们在显式ADER DG双曲PDE求解器ExaHyPE的背景下分析了后验极限程序的固有弹性。后验限制器检查元素局部高阶DG解决方案的物理可采性，因此可以期望也检测到硬件引起的错误。从算法上讲，它可以解释为在精细子网格上使用更健壮的有限体积方案进行求解器的元素局部检查点和重新启动。我们证明了限制器确实提高了DG算法的弹性，尤其是检测和纠正了那些会导致致命故障的故障。

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