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首页> 外文会议>IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain >Overcoming Challenges in Thermally Enhanced BGA Packaging with Low-k Silicon
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Overcoming Challenges in Thermally Enhanced BGA Packaging with Low-k Silicon

机译：克服采用低k硅的热增强BGA封装所面临的挑战

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All market segments continue to put cost pressure on semiconductor and packaging suppliers in order to stay competitive. Reducing silicon area while providing more silicon functionalities increases potential die count per wafer and lowers the die cost. Staying in wire bond packaging instead of migrating to flip chip packaging further provides a cost competitive advantage. Wire bond packaging for silicon devices has been the backbone of the semiconductor industry to serve communications and networking customers for many years. Innovative interconnect routing and IC design and fine pitch wire bonding capability enable silicon to have 900 bonding pads in an area of 60mm~2. The high wire count and wire density is unprecedented in thermally enhanced plastic ball grid array (PBGA) packages with an internal heat spreader, which is commonly denoted as TE-PBGA-II. With the further shrink of the silicon dimension, the Low-k inter-layer dielectric (ILD) material has been widely used to replace the traditional SiO_2 ILD in order to reduce the interconnect delay. Low-k dielectric by definition has a dielectric value of less than 3. The introduction of Low-k ILD material into the silicon process imposes new challenges for high wire density packaging. In particular, the inherently weak adhesion in the Low-k interconnect makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature cycling stress testing. This paper will discuss the challenges and resolution during the packaging development for Low-k products with high wire density in large 31×31 and 35×35mm TE-PBGA-II packages. Challenges range from wafer dicing through difficult test structures in the scribe streets, die attach fillet height control, wire bonding on Low-k bond pads, and molding Low-k silicon in a large package. Alternative methods including Finite Element Modeling and extended package reliability testing were used to demonstrate the robustness of the Low-k packaging solution.
机译：所有市场领域继续对半导体和封装供应商施加成本压力，以保持竞争力。在提供更多硅功能的同时减少硅面积可增加每个晶片的潜在芯片数量，并降低芯片成本。停留在引线键合封装中，而不是迁移到倒装芯片封装中，进一步提供了成本竞争优势。多年来，用于硅器件的引线键合封装一直是半导体行业的骨干，可为通信和网络客户提供服务。创新的互连布线和IC设计以及细间距引线键合功能使硅在60mm〜2的面积内具有900个键合焊盘。在带有内部散热器（通常称为TE-PBGA-II）的热增强塑料球栅阵列（PBGA）封装中，高线数和线密度是前所未有的。随着硅尺寸的进一步缩小，Low-k层间电介质（ILD）材料已被广泛用于替代传统的SiO_2 ILD，以减少互连延迟。根据定义，低k电介质的介电值小于3。将低k ILD材料引入硅工艺对高线密度封装提出了新的挑战。特别是，Low-k互连中固有的弱粘合性使硅更容易受到称为ILD裂纹或分层的故障模式的影响，该模式会在温度循环应力测试期间导致电气故障。本文将讨论采用31×31和35×35mm大型TE-PBGA-II封装的高线密度低k产品在包装开发过程中的挑战和解决方案。挑战包括晶圆切割，划线道中的困难测试结构，管芯附着圆角高度控制，Low-k键合焊盘上的引线键合以及在大封装中成型Low-k硅。包括有限元建模和扩展包装可靠性测试在内的替代方法被用来证明Low-k封装解决方案的耐用性。

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