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首页> 外文会议>IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain >Wafer Level Packaging: Balancing Device Requirements and Materials Properties
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Wafer Level Packaging: Balancing Device Requirements and Materials Properties

机译：晶圆级包装：平衡设备要求和材料属性

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Wafer level packaging for MEMS devices in the front end has a field proven history that now allows for these techniques to facilitate back end packaging and device integration. The most common methods for MEMS assembly include anodic and glass frit bonding which comprise more than 70-80% of all volume manufacturing processing today. However, metal based bonding schemes such as metal eutectics and metal diffusion seals provide increased hermeticity levels and facilitate inter-wafer and intra-device electrical connections. Adhesive bonds using a variety of materials types has been a long standing method for die to package assembly and over the past several years these techniques have been merged with metal techniques to enable wafer level 3D packaging.rnAt the same time that decisions are made regarding the choice of bonding methods it is necessary to consider the upstream and downstream processing. Integral to the success of the total packaging flow is balancing the thermal expansion issues of the various layers and substrates to minimize wafer bow and device stress. Understanding alignment requirements, hermeticity, and environmental requirements of the device must be met with the appropriate bond process flow.
机译：前端用于MEMS器件的晶圆级封装具有久经实践证明的历史，现在允许这些技术促进后端封装和器件集成。 MEMS组装的最常见方法包括阳极和玻璃粉粘结，这占当今所有批量制造工艺的70-80％以上。然而，诸如金属共晶和金属扩散密封之类的基于金属的结合方案提供了增加的气密性水平并且促进了晶片间和器件内的电连接。使用各种材料类型的胶粘剂粘合一直是用于芯片到封装组装的长期方法，并且在过去的几年中，这些技术已与金属技术合并以实现晶圆级3D封装。选择粘接方法时，有必要考虑上游和下游加工。总封装流程成功与否的关键在于平衡各个层和基板的热膨胀问题，以最大程度地减少晶圆弯曲和器件应力。必须以适当的键合工艺流程满足对设备的对准要求，气密性和环境要求的了解。

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