• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>IMAPS 2008 - 41st international symposium on microelectronics: bringing together the entire microelectronics supply chain >Optimization of Redistributed Layers between Heterogeneous Devices for Wafer-Level Integration
【24h】

Optimization of Redistributed Layers between Heterogeneous Devices for Wafer-Level Integration

机译：晶圆级集成的异构设备之间的重新分布层的优化

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Pseudo-SOC (System on Chip) technology is integration technology consisting of the chips embedded in epoxy resin and redistributed (thin-film metal) layer formed with semiconductor process, realizing the complementary advantages of SOC and SIP (System in Package) technology. In this technology, high-density integration is achieved by integrating heterogeneous chips with very narrow gap in the resin and without interposer substrate. In this paper, the authors focused on the improvement in the pitch of the redistributed layer by improving the planarization and the adhesivity of the underlying layer. By improving the transfer process of the chips and the printing process of the resin, the resin was formed between the chips set with narrow gap of 100μm with good filling ratio. Furthermore, by cont rolling the formation condition of the planar layer, redistributed layer with a fine pitch of 15μm/15μm in line and space was achieved. Thus, the redistributed layer with a pitch 3 times finer than that of the device previously developed was realized, leading to the miniaturization of pseudo-SOC.
机译：伪SOC（System on Chip，片上系统）技术是一种集成技术，由嵌入环氧树脂的芯片和采用半导体工艺形成的再分布（薄膜金属）层组成，从而实现了SOC和SIP（System in Package，封装系统）技术的互补优势。在该技术中，通过在树脂中插入间隙非常窄且没有插入基板的异质芯片来实现高密度集成。在本文中，作者专注于通过改善底层的平坦性和粘合性来改善重新分布层的间距。通过改善芯片的转移过程和树脂的印刷过程，在芯片组之间以100μm的窄缝隙形成了具有良好填充率的树脂。此外，通过连续轧制平面层的形成条件，可以得到线间距和间距为15μm/15μm的细间距的再分布层。因此，实现了间距比先前开发的器件的间距细3倍的重新分布层，从而导致了伪SOC的小型化。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号