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首页> 外文会议>Industrial Electronics (ISIE), 2012 IEEE International Symposium on >Frequency Locked Loop for grid-connected VSI synchronization and power analysis
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Frequency Locked Loop for grid-connected VSI synchronization and power analysis

机译：锁频环用于并网的VSI同步和功率分析

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Future power systems will include the massive utilization of distributed generation mainly based on renewable energy resources. These renewable energy resources can be interconnected to the utility grid by means of power electronics converters working as Voltage Source Inverters (VSIs) which must be synchronized with the utility voltage. Synchronization methods are mandatory to make possible a correct power control and to keep an acceptable power quality. The Field Programmable Gate Array (FPGA) has been introduced in recent years as a promising target device for embedded applications especially when the parallel implementation of multiple algorithms is needed. This paper presents a new structure of the Adaptive Linear Neuron (ADALINE) with Frequency Locked Loop (ADALINE-FLL), its FPGA implementation and its experimental evaluation. The proposition has been implemented in a Xilinx FPGA device and experimentally validated using low power VSI connected to a low voltage utility.
机译：未来的电力系统将主要基于可再生能源来大规模利用分布式发电。这些可再生能源可以通过用作电压源逆变器（VSI）的电力电子转换器与公用电网互连，必须与公用电压同步。必须使用同步方法才能进行正确的电源控制并保持可接受的电源质量。近年来，现场可编程门阵列（FPGA）成为嵌入式应用的有希望的目标设备，尤其是在需要并行实现多种算法的情况下。本文介绍了一种具有锁频环的自适应线性神经元（ADALINE）的新结构，其FPGA实现和实验评估。该提议已在Xilinx FPGA器件中实现，并使用连接至低压设备的低功耗VSI经过实验验证。

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