Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors

机译：嵌入式处理器上VC-1 / H.264 / AVS视频解码器的优化

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In this paper we propose some optimization techniques to achieve the goal of real-time decoding of the new generation video such as VC-1, H.264, and AVS on embedded processors. We optimize the VC-1/H.264/AVS video decoders from a variety of viewpoints including algorithmic complexity reduction, memory access minimization, branch minimization, and zero skipping. We have reduced about 80% ~ 90% of complexity after optimization with the proposed techniques as compared to the original reference codes. The proposed low complexity new generation video decoders can achieve about CIF@12fps ~ 14fps and QCIF@47 ~ 50fps when running on ARM9 processor at 200 MHz.

机译：在本文中，我们提出了一些优化技术来实现对嵌入式处理器上的VC-1，H.264和AVS等新一代视频进行实时解码的目标。我们从各种角度优化VC-1 / H.264 / AVS视频解码器，包括算法复杂度降低，内存访问最小化，分支最小化和零跳过。与原始参考代码相比，使用建议的技术进行优化后，我们降低了约80％〜90％的复杂度。当在200 MHz的ARM9处理器上运行时，建议的低复杂度新一代视频解码器可以实现大约CIF @ 12fps〜14fps和QCIF @ 47〜50fps。

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来源
《International Conference on Information Technology: New Generations;ITNG '09》|2009年|1313-1318|共6页
会议地点 Las Vegas NV(US);Las Vegas NV(US)
作者
Guo-An Jian; Ting-Yu Huang; Jui-Chin Chu; Jiun-In Guo;
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Dept. of Comput. Sci. Inf. Eng., Nat. Chung Cheng Univ., Chia-Yi;

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code standards; computational complexity; data compression; decoding; embedded systems; microprocessor chips; minimisation; video coding; ARM; VC-1/H.264/AVS video decoder; algorithmic complexity reduction; branch minimization; embedded processor; memory access minimization; new generation video; optimization technique; video compression; zero skipping; software optimization;

机译：代码标准;计算复杂度;数据压缩;解码;嵌入式系统;微处理器芯片;最小化;视频编码; ARM; VC-1 / H.264 / AVS视频解码器;算法复杂度降低;分支最小化;嵌入式处理器;内存访问最小化;新一代视频；优化技术；视频压缩；零跳跃；软件优化;

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专利

1. Cost-Effective Hardware-Sharing Design of Fast Algorithm Based Multiple Forward and Inverse Transforms for H.264/AVC, MPEG-1/2/4, AVS, and VC-1 Video Encoding and Decoding Applications [J] . IEEE Transactions on Circuits and Systems for Video Technology . 2014,第4期

机译：适用于H.264 / AVC，MPEG-1 / 2/4，AVS和VC-1视频编码和解码应用的基于快速算法的多重正反变换的经济高效的硬件共享设计
2. Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism [J] . Circuits, Devices & Systems, IET . 2010,第2期

机译：基于宏块行级并行性的高效H.264和VC-1视频解码多核平台
3. Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor [J] . Jin Ho Han, Mi Young Lee, Younghwan Bae, ETRI journal . 2005,第5期

机译：具有可配置嵌入式处理器的H.264解码器的专用处理器设计
4. Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors [C] . Guo-An Jian, Ting-Yu Huang, Jui-Chin Chu, International Conference on Information Technology: New Generations . 2009

机译：嵌入式处理器上VC-1 / H.264 / AVS视频解码器的优化
5. Optimization of H.264 baseline decoder on ARM9TDMI processor. [D] . Basavanahalli Sheshadri, Sandya. 2005

机译：在ARM9TDMI处理器上优化H.264基线解码器。
6. A Data Hiding Technique to Synchronously Embed Physiological Signals in H.264/AVC Encoded Video for Medicine Healthcare [O] . Raul Peña, Alfonso Ávila, David Muñoz, -1

机译：一种在医疗保健的H.264 / AVC编码视频中同步嵌入生理信号的数据隐藏技术
7. Parallel H.264 Decoding on an Embedded Multicore Processor [O] . Azevedo Arnaldo, Meenderinck Cor, Juurlink Ben, 2009

机译：嵌入式多核处理器上的并行H.264解码

Optimization of VC-1/H.264/AVS Video Decoders on Embedded Processors

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