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Design of multinode reconfigurable multiprocessor network for embedded systems

机译：嵌入式系统的多节点可重构多处理器网络设计

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In the realm of modern communication, embedded systems are the brains of about all computerized and modern control frameworks. Current computerized frameworks require increasingly electronic assets, so multiprocessor stages are an appropriate answer for them, conveying better surface, speed, and power utilization than ordinary monoprocessor advanced frameworks. Reconfigurable multiprocessor frameworks are a specific kind of embedded framework, actualized utilizing reconfigurable equipment. Advances in Field Programmable Gate Array (FPGA) technology are more powerful processing and adaptable systems. Adaptability is one of the qualities of this sort of framework, and multiprocessor frameworks can likewise be reconfigured at run time, enabling equipment to adjust to application needs. Multiprocessor-based chip frameworks (MPSoCs) speak to a noteworthy pattern in the inherent advanced gadgets. Although hardware support for parallel computing is increasingly available in embedded computing platforms, there is a clear lack of effective software support. A standout amongst the most essential issues with respect to these frameworks is correspondence between processors. Presently correspondence in a few controllers should be possible for the most part by two visual conventions. I2C and SPI. But there are some limitations of these two protocols described in this document and how can it be overcome by using our proposed protocol also mentioned in this document. This document proposed another strategy for correspondence for a multi-secluded Embedded framework. The parallel design is adjusted and hence is the quickest approach to impart. Also, it provides a detailed description of the Distributed Computing of the Integrated Communication Re-Configurable Agreement between multiprocessors and investigating for its merits and demerits.
机译：在现代通信领域，嵌入式系统是所有计算机化和现代控制框架的大脑。当前的计算机化框架需要越来越多的电子资产，因此多处理器阶段是对它们的适当解决方案，与普通的单处理器高级框架相比，它具有更好的表面，速度和功耗。可重配置的多处理器框架是一种特定的嵌入式框架，是利用可重配置的设备实现的。现场可编程门阵列（FPGA）技术的进步是更强大的处理能力和适应性更强的系统。适应性是这种框架的特质之一，多处理器框架同样可以在运行时重新配置，从而使设备能够适应应用程序的需求。基于多处理器的芯片框架（MPSoC）在固有的高级小工具中具有明显的意义。尽管嵌入式计算平台越来越多地提供对并行计算的硬件支持，但是显然仍然缺乏有效的软件支持。关于这些框架，最重要的问题之一是处理器之间的对应关系。目前，在大多数情况下，通过两个视觉约定，应该可以在几个控制器中进行通信。 I2C和SPI。但是，本文档中介绍的这两种协议存在一些局限性，并且如何使用本文档中也提到的建议协议来克服它。该文档提出了针对多隔离嵌入式框架的另一种通信策略。并行设计已调整，因此是最快的实现方法。此外，它还提供了多处理器之间集成通信可重新配置协议的分布式计算的详细说明，并对其优缺点进行了调查。

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