Vlsi Design Of Low Power Data Encoding Techniques For Network-On-Chip

机译：网络上网电源数据编码技术的VLSI设计

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As technology improves, the power dissipated by the links of a network-on-chip (NoC) starts to contend with the power dissipated by the additional elements of the correspond ion subsystem, namely, the routers and the network interfaces (NIs). Here, we present a set of data encoding schemes to diminish the power dissipated by the links of an NoC. In this paper, the encoder in LDPC is replaced with our data encoding schemes in order to reduce the power consumption in Low Density Parity Check Techniques. Experiments carried out on both synthetic and real traffic scenarios show the effectiveness of the proposed schemes.

机译：随着技术的改进，由片上网络（NOC）的链接消耗的功率开始与对应离子子系统的附加元件，即路由器和网络接口（NIS）争辩的功率。在这里，我们提出了一组数据编码方案来减少由NOC的链接消耗的功率。在本文中，利用我们的数据编码方案替换了LDPC中的编码器，以降低低密度奇偶校验技术中的功耗。在合成和实际交通方案上进行的实验表明了提出的方案的有效性。

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《International Conference on Signal Processing, Communication, Power and Embedded System》|2016年|1423-2124p|共5页
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G. Sravya; M. Sailaja;
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中图分类 TN91-53;
关键词
Data encoding; Interconnection on chip; Low density parity check; Majority logic decoding; Power analysis;

机译：数据编码;芯片互连;低密度奇偶校验;多数逻辑解码;功率分析;

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1. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip [J] . Ruchira Ganesh Waghmare, Suhas Sayajirao Jadhav International Journal of Engineering Research and Applications . 2018,第1期

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2. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip [J] . IEEE transactions on very large scale integration (VLSI) systems . 2014,第3期

机译：降低片上网络能耗的数据编码技术
3. Variable-to-Variable Run Length Encoding Technique for Testing Low Power VLSI Circuits [J] . Lakshmi K, Robert Theivadas J, Markk, Journal of Electrical & Electronic Systems . 2019,第1期

机译：用于测试低功耗VLSI电路的可变到可变游程长度编码技术
4. Vlsi design of low power data encoding techniques for network-on-chip [C] . G. Sravya, M. Sailaja International Conference on Signal Processing, Communication, Power and Embedded System . 2016

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5. Computer aided design techniques for network-on-chip architectures and system-level low power optimization. [D] . Srinivasan, Krishnan. 2006

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7. Study of Ultra Low Power Design and Power Reduction Techniques for VLSI Circuits at Ultra Low Voltages [O] . Varanasi Phani Kameswara Abhishikth 2015

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8. A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology [R] . Fang, W. C., Lin, T. H. 1999

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Vlsi Design Of Low Power Data Encoding Techniques For Network-On-Chip

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