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Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer

机译：使用异质结埋层消除手指型ESD保护晶体管的非同时触发效应

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This paper presents a novel technique to eliminate non-simultaneous triggering effects in finger-type ESD protection transistor using SiGe heterojunction buried layer structures. It is confirmed that lower snapback voltage and maximum lattice temperature are obtainable in the new structure based on device simulation. As a result, current localization and lattice overheating of a finger-type protection transistor caused by process variations can be avoided in this structure.

机译：本文提出了一种新颖的技术，可消除使用SiGe异质结埋层结构的手指型ESD保护晶体管的非同时触发效应。基于器件仿真，可以确认在新结构中可以获得较低的骤回电压和最高晶格温度。结果，在该结构中，可以避免由于工艺变化而引起的手指型保护晶体管的电流局部化和晶格过热。

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来源
《》|1998年|304-307|共4页
会议地点 Leuven(BE);Leuven(BE)
作者
Chang-Hoon Choi; Zhiping Yu; Robert W. Dutton;
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作者单位

Center for Integrated Systems Stanford University Stanford, CA. 94305, USA;

Center for Integrated Systems Stanford University Stanford, CA. 94305, USA;

Center for Integrated Systems Stanford University Stanford, CA. 94305, USA;

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原文格式 PDF
正文语种 eng
中图分类半导体器件制造工艺及设备;
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专利

1. Novel ESD protection transistor including SiGe buried layer to reduce local temperature overheating [J] . Chang-Hoon Choi, Young-Kwan Park IEEE Transactions on Electron Devices . 1996,第3期

机译：新型ESD保护晶体管，包括SiGe埋层，可减少局部温度过热
2. Effects of buried oxide layer on working speed of SiGe heterojunction photo-transistor [J] . Xian-Cheng Liu, Jia-Jun Ma, Hong-Yun Xie, 中国物理：英文版 . 2020,第002期

机译：掩埋氧化物层对SiGe异质结光电晶体管工作速度的影响
3. p-n-p heterojunction bipolar transistors with buried subcollector layers [J] . Bayraktaroglu B., Lambert S.A. IEEE Electron Device Letters . 1989,第3期

机译：具有埋藏子集电极层的p-n-p异质结双极晶体管
4. Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer [C] . Chang-Hoon Choi, Zhiping Yu, Robert W. Dutton International conference on simulation of semiconductor devices and processes . 1998

机译：使用异质结埋层消除手指型ESD保护晶体管中的非同时触发效果
5. Low loading capacitance on-chip electrostatic discharges (ESD) protection circuits for gallium arsenide heterojunction bipolar transistor (HBT) radio frequency integrated circuits (RFIC). [D] . Ma, Yintat. 2004

机译：用于砷化镓异质结双极晶体管（HBT）射频集成电路（RFIC）的低负载电容片上静电放电（ESD）保护电路。
6. Electrical Performance and Bias-Stress Stability of Amorphous InGaZnO Thin-Film Transistors with Buried-Channel Layers [O] . Ying Zhang, Haiting Xie, Chengyuan Dong 2019

机译：具有埋沟道层的非晶InGaZnO薄膜晶体管的电性能和偏压应力稳定性
7. Schottky Barrier Variable Graphene/Multilayer-MoS2 Heterojunction Transistor Used to Overcome Short Channel Effects [O] . -1

机译：肖特基屏障变量石墨烯/多层-MOS2异质结晶体管用于克服短信道效应
8. In0.69Al0.31As0.41Sb0.59/ In0.27Ga0.73Sb double-heterojunction bipolar transistors with InAs0.66Sb0.34 contact layers [R] . 2010

机译：In0.69al0.31as0.41sb0.59 / In0.27Ga0.73sb双异质结双极晶体管，带Inas0.66sb0.34接触层

Elimination of Non-Simultaneous Triggering Effects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer

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