The influence of multi-layer metal process on high-speed LSI characteristics becomes important. So, we have developed a CMP process model, incorporated it into the Selete TCAD system, and examined the impact to LSI characteristic variation. The simulation results of dielectric film thickness by CMP well agree with experiments within 5% errors in practical calculation time. It is found that capacitance variation in a LSI chip with CMP process is large enough according to LSI layout design.
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