首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >IMPROVEMENT IN GATE OXIDE USING LOW TEMPERATURE AR-PRECLEAN AND TI DEPOSITION FOR 0.18μm METALLIZATION
【24h】

IMPROVEMENT IN GATE OXIDE USING LOW TEMPERATURE AR-PRECLEAN AND TI DEPOSITION FOR 0.18μm METALLIZATION

机译:0.18μm镀层的低温Ar沉淀和TI沉积法改进门氧化物

获取原文

摘要

Plasma induced damage (PID) to gate oxides was investigated using transistor antenna yield as a function of processing temperature. In this paper, degradation of the gate oxide due to both Ar preclean and Ti deposition during contact metallization as a function of wafer temperature are presented for the first time. Antenna structures metallized with films deposited using low temperature Ar-preclean and low temperature Ti deposition had significantly higher yields than structures fabricated using higher temperature processing. Antenna yield was measured by gate oxide breakdown voltage and leakage current. Low temperature processing significantly improved the antenna yield due to reduced gate oxide damage. The process parameters responsible for gate oxide damage are identified and optimized, without sacrificing the contact resistance. High pressure and reactive sputter clean were also investigated and showed no effect on the plasma induced damage to the gate oxide.
机译:使用晶体管天线的产量与处理温度的函数,研究了对栅极氧化物的等离子体诱导损伤(PID)。在本文中,首次提出了在接触金属化过程中,由于Ar预清洗和Ti沉积而导致的栅极氧化物的劣化与晶片温度的关系。与使用高温工艺制造的结构相比,用低温Ar-preclean和低温Ti沉积的膜金属化的天线结构的成品率要高得多。通过栅氧化层击穿电压和泄漏电流来测量天线的良率。由于降低了栅极氧化层的损坏,低温处理大大提高了天线的良率。在不牺牲接触电阻的前提下,确定并优化了造成栅极氧化物损坏的工艺参数。还对高压和反应性溅射清洁进行了研究,结果表明对等离子体诱导的栅氧化层损伤没有影响。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号