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首页> 外文会议>International VLSI multilevel interconnection conference;VMIC >3D Microstructural Simulation of Thin Film Deposition for VLSI Interconnects
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3D Microstructural Simulation of Thin Film Deposition for VLSI Interconnects

机译：用于VLSI互连的薄膜沉积的3D微结构仿真

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This paper reports the use of a novel 3D simulator - 3D-Films - which simulates the creation and growth of three dimensional microstructure in vapour deposited refractory films. The simulator produces a detailed depiction of the film, including grain and columnar structure and is capable of producing density and porosity information. This paper first presents the basic program structure, discussing issues of memory management, growth modeling, visualization and post processing. To determine the validity of the microstructural modeling porous GLAD films are simulated. The simulator is then used to address a number of issues; including deposition over dual damascene structures, barrier layer deposition over trenches and vias, with comparison to 2D simulation. Finally the program is used to look at the effect of topography on liner overhang creation and subsequent CVD filling of high aspect ratio features.
机译：本文报道了新型3D仿真器3D-Films的使用，该仿真器可模拟气相沉积耐火膜中三维微观结构的产生和增长。该模拟器对薄膜进行了详细的描绘，包括晶粒和柱状结构，并且能够产生密度和孔隙率信息。本文首先介绍了基本程序结构，讨论了内存管理，增长建模，可视化和后处理等问题。为了确定微观结构建模的有效性，对多孔GLAD薄膜进行了模拟。然后使用模拟器来解决许多问题。与2D模拟相比，包括双镶嵌结构上的沉积，沟槽和通孔上的势垒层沉积。最后，该程序用于查看地形对衬套悬垂的产生以及随后的高纵横比特征的CVD填充的影响。

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