Incremental Circuit Simulation for Large-Scale MOSFET Circuits with Interconnects Using Iterated Timing Analysis

机译：使用迭代时序分析的带互连的大型MOSFET电路的增量电路仿真

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The circuit level incremental simulation is a good strategy to reduce the circuit simulation time, since most circuit designers use circuit simulators to simulate incrementally modified circuits repeatedly. This paper researches the large-scale incremental circuit simulation using the well-known ITA (Iterated Timing Analysis) algorithm. The target circuits are popular MOSFET circuits containing interconnects that are modeled by transmission lines. This paper has proposed an efficient algorithm for incremental simulation, the method to handle transmission lines, and other time-saving techniques. Experimental results justify that proposed methods undertake large-scale incremental circuit simulation for MOSFET and transmission lines very well.

机译：电路级增量仿真是减少电路仿真时间的好策略，因为大多数电路设计人员都使用电路仿真器来反复仿真增量修改的电路。本文使用众所周知的ITA（迭代时序分析）算法研究大规模增量电路仿真。目标电路是流行的MOSFET电路，其中包含通过传输线建模的互连。本文提出了一种高效的增量仿真算法，处理传输线的方法以及其他节省时间的技术。实验结果证明，所提出的方法可以很好地对MOSFET和传输线进行大规模的增量电路仿真。

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《International conference on electric and electronics;EEIC 2011》|2011年|p.557-562|共6页
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Chen Chun-Jung;
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正文语种
中图分类通信;
关键词
circuit simulation; relaxation-based algorithms; incremental simulation; iterated timing analysis; transmission line.;

机译：电路仿真基于松弛的算法;增量模拟迭代时序分析;传输线。;

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2. From Circuit Theory, Simulation to SPICEDiego: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits [J] . Hao Zhuang, Xinyuan Wang, Quan Chen, IEEE circuits and systems magazine . 2016,第2期

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3. Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations [J] . Li B., Chen N., Schlichtmann U. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2012,第11期

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4. Incremental Circuit Simulation for Large-Scale MOSFET Circuits with Interconnects Using Iterated Timing Analysis [C] . Chen Chun-Jung International Conference on Electric and Electronics . 2011

机译：使用迭代时序分析与互连大型MOSFET电路的增量电路仿真
5. Incremental circuit simulation and timing analysis techniques [D] . Ju, Yun-Cheng 1992

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6. Electrically driven monolithic subwavelength plasmonic interconnect circuits [O] . Yang Liu, Jiasen Zhang, Huaping Liu, 2017

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7. Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance [O] . Soens, C., Van Der Plas, G., Wambacq, P., 2007

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8. Switch-Level Timing Simulation of MOS VLSI (Metal-Oxide-Semiconductor Very Large-Scale Integrated) Circuits. [R] . Rao, V. B. 1985

机译：mOs VLsI（金属氧化物半导体超大规模集成电路）的开关级时序仿真。

Incremental Circuit Simulation for Large-Scale MOSFET Circuits with Interconnects Using Iterated Timing Analysis

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