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首页> 外文会议>2011 Seventh ACM/IEEE Symposium on Architectures for Networking and Communications Systems >A Canonical Multicore Architecture for Network Routers
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A Canonical Multicore Architecture for Network Routers

机译：网络路由器的典型多核体系结构

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There has been a significant increase in the Internet dynamics in the past decade. This has put tremendous pressure on the performance of routing protocols as they need to keep updating their routing information with every network change across the globe. With the growth of Internet, Border Gateway Protocol (BGP) has become a critical routing application. Good performance of BGP on network processors directly translates to better convergence time for route changes on the Internet, leading to reduced data loss on the network. BGP is the ubiquitous routing protocol on the Internet core, and hence analyzing its performance and exploring avenues for speeding it up can greatly help in improving the responsiveness and reliability of the Internet. In this paper, we investigate the use of multicore as the compute platform for routing protocols using BGP as a representative application. We discuss two different schemes for parallelizing BGP and analyze the performance of both serial and parallel BGP implementations on a fully configurable multicore simulation environment. Subsequently, we analyze the architectural bottlenecks in the conventional multicore systems which limit the speedup that can be achieved by software parallelism alone, and propose a canonical multicore architecture for routing protocols, which can be used for future routing processor designs. The analysis and proposed schemes in this paper would greatly help in understanding the behavior of BGP, thereby assisting in design and development of next generation network processors.
机译：在过去的十年中，Internet的动态已大大增加。这给路由协议的性能带来了巨大压力，因为它们需要随着全球每一个网络的变化不断更新其路由信息。随着Internet的发展，边界网关协议（BGP）已成为关键的路由应用程序。 BGP在网络处理器上的良好性能直接转化为Internet上路由更改的收敛时间更长，从而减少了网络上的数据丢失。 BGP是Internet核心上无处不在的路由协议，因此分析它的性能并探索加速它的途径可以极大地帮助提高Internet的响应能力和可靠性。在本文中，我们研究使用多核作为以BGP为代表的路由协议的计算平台。我们讨论了使BGP并行化的两种不同方案，并分析了在完全可配置的多核仿真环境下串行和并行BGP实现的性能。随后，我们分析了传统多核系统中的架构瓶颈，这些瓶颈限制了仅通过软件并行性就可以实现的速度提升，并提出了一种用于路由协议的规范多核体系结构，该体系结构可用于未来的路由处理器设计。本文的分析和提出的方案将大大有助于理解BGP的行为，从而有助于下一代网络处理器的设计和开发。

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