Design and analysis of a low-power high-speed charge-steering based StrongARM comparator

机译：低功耗高速电荷转向基于Birtharm比较器的设计与分析

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This paper presents an ultra low-power high-speed dynamic comparator. The proposed dynamic comparator is designed and simulated in a 65-nm CMOS technology. It dissipates 7 μW, 21.1 μW from a 0.9-V supply while operating at 1 GHz, 3 GHz sampling clock respectively. Proposed circuit can work up to 14 GHz. Ultra low power consumption is achieved by utilizing charge-steering concept and proper sizing. Monte Carlo simulations show that the input referred offset contribution of the internal devices is negligible compared to the effect of the input devices which results in 3.8 mV offset and 3 mV kick-back noise.

机译：本文介绍了超低功耗高速动态比较器。所提出的动态比较器采用65nm CMOS技术设计和模拟。它分别在0.9-V电源处消散7μW，21.1μW，分别在1 GHz，3 GHz采样时钟运行。提出的电路可以工作高达14 GHz。通过利用电荷转向概念和适当的尺寸来实现超低功耗。蒙特卡罗模拟表明，与输入设备的效果相比，内部设备的输入偏移贡献可忽略不计，从而导致3.8 mV偏移和3个MV返回噪声。

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《International Conference on Microelectronics》|2016年|380 p.|共4页
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Mostafa M. Ayesh; Sameh Ibrahim; Mohamed M. Aboudina;
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正文语种
中图分类微模组件;
关键词
Delays; Power demand; Latches; Transistors; Clocks; Rails; Capacitors;

机译：延迟;电力需求;闩锁;晶体管;钟表;轨道;电容器;

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Design and analysis of a low-power high-speed charge-steering based StrongARM comparator

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