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首页> 外文期刊>Analog Integrated Circuits and Signal Processing >Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator
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Analysis and design of low-voltage low-power high-speed double tail current dynamic latch comparator

机译：低压低功耗高速双尾电流动态锁存器的分析与设计

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摘要

The demanding need of ultra-high speed, area efficient and power optimized analog-to-digital converter is forcing towards the exploration and usage of the dynamic regenerative comparator to minimize the power, area and maximize the speed. In this paper, detailed analysis of the delay for the various dynamic latch based comparators is presented and analytical expressions are derived. With the help of analytical expressions, the designer can obtain insight view of the different parameters, which are the contributors of the delay in the dynamic comparator. Based on the findings, various tradeoffs can be explored. Based on the literature and presented analysis, a new dynamic latch based comparator is proposed. The basic double tail dynamic latch based comparator and shared charge logic are modified for low-power and high-speed with the reduced power supply in the proposed comparator. With the modified structure of double tail latch comparator and adding the shared charge logic, the regeneration delay is reduced, at the same time, power consumption is also reduced. Simulation results in 90 nm CMOS technology confirm the claimed reductions. The simulation is carried out using 90 nm technology with a supply voltage of 1 V, at 1 GHz of frequency resulting into the delay of 50.9 ps while consuming 31.80 mu W of power.
机译：对超高速，面积高效和功率优化的模数转换器的苛刻需求迫使动态再生比较器的勘探和使用，以最大限度地减少功率，面积并最大化速度。本文提出了对各种动态锁存器基于比较器的延迟的详细分析，得到了分析表达。在分析表达式的帮助下，设计人员可以获得不同参数的洞察视图，这是动态比较器中延迟的贡献者。根据调查结果，可以探索各种权衡。基于文献和呈现的分析，提出了一种新的动态锁存器的比较器。基本双尾动态锁存器基于比较的比较器和共用充电逻辑被修改为低功耗和高速，在提出的比较器中的电源降低。随着双尾锁存器的改进结构并添加共享充电逻辑，再生延迟减少，同时也减少了功耗。 90 nm CMOS技术的仿真结果证实了要求保护的减少。使用90nm技术进行仿真，电源电压为1 V，在1 GHz的频率下，导致延迟为50.9 ps，同时消耗31.80亩。

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