Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

机译：Muller C元件自我校正的三重模块化冗余逻辑，具有多线程和低功耗模式

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This work describes voting feedback circuits for triple modular redundant (TMR) self-correcting flip-flops that reduce the flip-flop circuit area by 20% and the energy consumption by 10% over the conventional use of a majority gate. A fully pipelined 256-bit key and 128-bit data advanced encryption standard (AES) engine implemented at the 90 nm technology node using the proposed design and has a maximum performance of 400 MHz and 297 mW in TMR and multi-thread modes. It operates in a low-power, non-redundant mode at 102 mW power dissipation. Testability modes are are also described.

机译：这项工作描述了用于三重模块化冗余（TMR）自校正触发器的投票反馈电路，其在传统使用多数门的传统使用中将触发器电路区域减少20％，并且能量消耗量为10％。使用所提出的设计，在90 nm技术节点中实现的完全流水线的256位键和128位数据高级加密标准（AES）发动机，并且在TMR和多线程模式下具有400 MHz和297 MW的最大性能。它以102 MW功耗为低功耗，非冗余模式运行。还描述了可测试模式。

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《European Conference on Radiation and Its Effects on Components and Systems》|2017年|549p|共4页
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C. Ramamurthy; A. Gujja; V. Vashishtha; Srivatsan Chellappa; L. T. Clark;
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原文格式 PDF
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中图分类 TN014-53;
关键词
Latches; Clocks; Logic gates; Pipelines; Flip-flops; Standards; Layout;

机译：闩锁;时钟;逻辑门;管道;触发器;标准;布局;

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1. Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic [J] . Hindman N. D., Clark L. T, Patterson D. W., Nuclear Science, IEEE Transactions on . 2011,第6期

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2. Low-Power Reed-Muller Logic Standard Cells and Their Dual Logic Mappings [J] . Haotian Zhu, Jianping Hu, Tianfang Ma, Journal of Residuals Science & Technology . 2016,第6期

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3. A Low-Power Quadrature Local Oscillator Using Current-Mode-Logic Ring Oscillator and Frequency Triplers [J] . Lin Y.-S., Hsu C.-W., Lu C.-L., IEEE microwave and wireless components letters . 2013,第12期

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4. Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes [C] . C. Ramamurthy, A. Gujja, V. Vashishtha, European Conference on Radiation and Its Effects on Components and Systems . 2017

机译：具有多线程和低功耗模式的Muller C元素自校正三重模块冗余逻辑
5. Delay/power modeling and optimization techniques for low-power FinFET logic circuits and architectures. [D] . Tang, Aoxiang. 2015

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7. Compact and power efficient MOS-NDR muller C-elements [O] . Núñez, Juan, Avedillo, M. J., Quintana, J. M. 2013

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8. Effects of Race Conditions when Implementing Single-Source Redundant Clock Trees in Triple Modular Redundant Synchronous Architectures. [R] . Berg, M. D., Label, K. A., Pellish, J. 2016

机译：三模冗余同步架构中实现单源冗余时钟树时竞争条件的影响。

Muller C-element Self-corrected Triple Modular Redundant Logic with Multithreading and Low Power Modes

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