The dual logic circuits based on Boolean Logic (TB) and Reed-Muller (RM) can obtain more results than alone TB or RM. In this paper, low-power RM logic standard cells are developed. The RM standard cells are optimized by using gate-length biasing (GLB) and dual-threshold (DG) techniques to achieve low power delay product (PDP). The layout design and description models for commercial EDA tools are also described. In order to show energy efficiency of the proposed standard cells, dual logic mapping based on the TB and RM standard cells are illustrated. An example is verified with the proposed RM cells. All circuits are simulated with HSPICE at SMIC 130nm CMOS technology by a 1.2V supply voltage at 100MHz. The results indicate the proposed RM cells are a good choice in energy-efficient designs.
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