Dual-rail improved adiabatic pseudo-domino logic with auxiliary clock: a low-power partially-adiabatic CMOS logic family

W. M. Tan; K. T. Lau

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Dual-rail improved adiabatic pseudo-domino logic with auxiliary clock: a low-power partially-adiabatic CMOS logic family

机译：具有辅助时钟的双轨改进的绝热伪多米诺逻辑：低功耗部分绝热CMOS逻辑系列

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An improved structure for adiabatic pseudo-domino logic (APDL) family is presented in this paper. The modified dual-rail improved APDL (MDIAPDL) exhibits lower power dissipation than the conventional static CMOS as shown in HSpice simulations. Comprehensive circuit simulations show that the MDIAPDL 4 bit shift register can recover over 95 per cent of the energy dissipated in conventional static CMOS 4 bit shift register.

机译：本文提出了一种改进的绝热伪多米诺逻辑（APDL）系列结构。改进的双轨改进型APDL（MDIAPDL）与传统的静态CMOS相比具有更低的功耗，如HSpice仿真所示。全面的电路仿真显示，MDIAPDL 4位移位寄存器可以恢复传统静态CMOS 4位移位寄存器中95％以上的能量消耗。

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《Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe》 |2003年第2期|共3页
作者
W. M. Tan; K. T. Lau;
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正文语种 eng
中图分类微电子学、集成电路（IC）;
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electrical circuits; design;

机译：电路;设计;

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1. Dual-rail improved adiabatic pseudo-domino logic with auxiliary clock: a low-power partially-adiabatic CMOS logic family [J] . W. M. Tan, K. T. Lau Microelectronics international: Journal of ISHM--Europe, the Microelectronics Society--Europe . 2003,第2期

机译：具有辅助时钟的双轨改进的绝热伪多米诺逻辑：低功耗部分绝热CMOS逻辑系列
2. Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic [J] . Michio Yokoyama, Seong-Kweon Kim, Seung-Il Cho, IEICE Electronics Express . 2013,第20期

机译：绝热动态CMOS逻辑与交流电源同步的低功耗时钟发生器的设计
3. Analysis of improved adiabatic pseudo-domino logic family [J] . Patel D.C., Morton E.J. Electronics Letters . 1998,第19期

机译：改进的绝热伪多米诺逻辑家族分析
4. Clocked CMOS adiabatic logic with low-power dissipation [C] . Li He, Zhang Yimeng, Yoshihara Tsutomu International SoC Design Conference . 2013

机译：具有低功耗的时钟CMOS绝热逻辑
5. IDPAL -- a partially-adiabatic energy-efficient logic family: Theory and applications to secure computing. [D] . Cutitaru, Mihail T. 2014

机译：IDPAL-绝热节能逻辑家族：安全计算的理论与应用。
6. Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device [O] . Yinhua Cui, Jeong Yeul Jeong, Yuan Gao, 2020

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7. Low-voltage single-phase clocked quasi-adiabatic pass-gate logic family for low-power submicron VLSI CMOS applications [O] . Loo Edward K. W. 2007

机译：适用于低功耗亚微米VLSI CMOS应用的低压单相时钟准绝热传递门逻辑系列
8. Electron Lithography STAR Design Guidelines. Part 3: The Mosaic Transistor Array Applied to Custom Microprocessors. Part 4: Stores Logic Arrays, SLAS Implemented with Clocked CMOS [R] . Trotter, J. D. 1982

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Dual-rail improved adiabatic pseudo-domino logic with auxiliary clock: a low-power partially-adiabatic CMOS logic family

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