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Constraint-Based Placement and Routing for FPGAs Using Self-Organizing Maps

机译：使用自组织地图的基于约束的展示位置和FPGA的路由

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Field-programmable gate arrays (FPGAs) are becoming increasingly popular due to low design times, easy testing and implementation procedures and low costs. FPGAs placement and routing are NP-complete problems dealt well with modern tools using heuristic algorithms. As modern FPGAs increase in size and also new capabilities, such as Run-Time Reconfiguration (RTR), are introduced, the complexity of these problems is greatly increased. In this paper we approach both problems using a modified version of Kohonen Self-Organizing map. The algorithm, consisting of four phases, takes into consideration constraints that may apply to the FPGA design (such as I/O pins, resource constraints like global clock etc). The modified algorithm yields a good topological map of the design to be placed, minimizing the average distance between connecting logic blocks.
机译：现场可编程门阵列（FPGA）由于低设计时间，易于测试和实现程序和低成本而变得越来越受欢迎。 FPGA放置和路由是使用启发式算法的现代工具良好的NP完整问题。由于介绍了现代FPGA的规模和新功能，如运行时间重新配置（RTR），这些问题的复杂性大大增加。在本文中，我们使用经过修改的Kohonen自组织地图来解决这两个问题。由四个阶段组成的算法考虑了可能适用于FPGA设计的约束（例如I / O引脚，像全局时钟等资源约束）。修改的算法产生要放置的设计的良好拓扑图，最小化连接逻辑块之间的平均距离。

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