Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low power SRAM design as an alternative material to silicon in recent years. However, tube misalignment problem obstructs the application of CNFET to large scale integration. In this paper, we propose a design method for 6T CNFET misalignment immune SRAM circuit. By vulnerability analysis of a basic layout, drain to source short, source to source short and wrong gate control problems due to tube misalignment are found. Then, misalignment immune layout for 6T CNFET SRAM cell is proposed by defining etching region. Steps for misalignment immune circuit fabrication and design considerations for tube number are given. Finally, HSPICE simulation demonstrates that the proposed 6T CNFET SRAM cell design achieves 84.21% reading power-delay product (PDP) reduction and 22.12% writing PDP reduction, 36.07% static noise margin and 117.63% read noise margin improvement in terms of stability, and 29.01% cell area reduction compared with its CMOS counterpart under 32nm technology.
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