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首页> 外文会议>IEEE International Midwest Symposium on Circuits and Systems >Ultra Low Power Multi-Operand Adder Architecture for Subthreshold Circuits
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Ultra Low Power Multi-Operand Adder Architecture for Subthreshold Circuits

机译：用于亚阈值电路的超低功耗多功能Adder架​​构

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摘要

Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V_(dd) < V_(th)), one of the important consideration is to improve the energy efficiency of the digital circuits through lowering the minimum energy point. In this paper, we propose a Ultra Low Power Multi Operand Adder (ULP-MOA) architecture capable of operating at subthreshold voltages. Using SPICE simulation, we have evaluated the energy and delay performance of the proposed ULP-MOA architecture and compared them with various traditional multi operand adder architectures. We show that the proposed adder architecture has lower optimal voltage point and less energy consumption; e.g. 7 operands, 8 bits consume 13.7 f J at 250mV when compared with the same size traditional ripple carry adder based multi operand adder (RC-MOA) that consumes 22.4 f J at 300mV; representing 63% net energy saving per multi operand addition. In addition, the proposed ULP-MOA has lower delay (271ns) than the RC-MOA (292ns) and same area overhead (1728 transistors).
机译：如果电路延迟增加是次要的，则亚阈值逻辑可以显着降低能量消耗。为了获得这种设计技术的广泛采用（其中V_（DD）

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