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Design and Implementation of High-Speed Real-Time Communication Architecture for PC-Based Motion Control System

机译：基于PC的运动控制系统高速实时通信架构的设计与实现

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摘要

To enhance the efficiency and stability of real-time data acquisition and transmission in motion control process, a high-speed realtime communication architecture based on FPGA and DSP is developed in this paper. The direct-memory-access (DMA) control module initiates DMA transfers over the peripheral-component-interconnect (PCI) bus. After that, two first-in-first-out (FIFO) buffers work as caches and convert data widths between the PCI bus and the local bus. Consequently, the data caches can be accessed by DSP over the local bus under DMA mode. The size of data transferred each time is able to be adjusted according to the application requirements. Experiments are carried out to demonstrate that the proposed communication architecture is capable of achieving high speed and stability in data communication with low consumption of compute resources.
机译：为了提高运动控制过程中实时数据采集与传输的效率和稳定性，本文开发了一种基于FPGA和DSP的高速实时通信架构。直接内存访问（DMA）控制模块通过外围组件互连（PCI）总线启动DMA传输。之后，两个先进先出（FIFO）缓冲区用作高速缓存，并在PCI总线和本地总线之间转换数据宽度。因此，DSP可以在DMA模式下通过本地总线通过DSP访问数据高速缓存。每次传输的数据大小都可以根据应用需求进行调整。实验表明，所提出的通信体系结构能够以较低的计算资源消耗实现数据通信的高速和稳定。

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