An analytical model for evaluating the influence of device parasitics on Cdv/dt induced false turn-on in SiC MOSFETs

机译：用于评估器件寄生对CDV / DT诱导SIC MOSFET的假开启的分析模型

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Reported here is an analytical methodology for modeling the Cdv/dt induced false turn-on in SiC MOSFETs. A Cdv/dt test circuit is utilized to assess the influence of the parasitic device parameters on the magnitude of the induced gate-source voltage during false turn-on. The effect that each parasitic parameter has on the damping of the SiC MOSFET's drain-source voltage is also evaluated. Experimental results are provided to validate the analytical model. The methods presented here will enable design engineers to project the performance of next generation SiC MOSFETs in high dv/dt circuits like the synchronous buck converter.

机译：这里报道了一种用于在SiC MOSFET中建模CDV / DT诱导的假开启的分析方法。 CDV / DT测试电路用于评估寄生装置参数在假开启期间对感应栅极源电压的大小的影响。还评估了每个寄生参数对SiC MOSFET漏极源电压的阻尼的影响。提供实验结果以验证分析模型。此处提供的方法将使设计工程师能够将下一代SIC MOSFET的性能投影在类似于同步降压转换器的高DV / DT电路中的性能。

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《Annual IEEE Applied Power Electronics Conference and Exposition》|2013年||共8页
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Khanna Raghav; Amrhein Andrew; Stanchina William; Reed Gregory;
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原文格式 PDF
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中图分类 TM1-53;
关键词
Cdv/dt; False turn-on; SiC MOSFET; damping; switching loss;

机译：CDV / DT;假开启;SIC MOSFET;阻尼;切换损耗;

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专利

1. A New Analytical Model for Predicting $dv/ dt$-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters [J] . Li Ruqi, Zhu Qiuhua, Xie Manjing IEEE Transactions on Power Electronics . 2019,第6期

机译：预测 $ dv / dt $ 引起的低侧MOSFET虚假导通的新分析模型在同步降压转换器中
2. A New Analytical Model for Predicting $dv/ dt$-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters [J] . Li Ruqi, Zhu Qiuhua, Xie Manjing IEEE Transactions on Power Electronics . 2019,第6期

机译：一种新的预测 $ dv / dt $ 诱导的低端MOSFET错误开启降压转换器
3. Modeling of Power MOSFET with Parasitic Parameters for the Analysis of Cdv/dt Induced Effects in Power Converters [J] . Shen Xu, Xia Liu, Haixiang Gao IETE Journal of Research . 2011,第3期

机译：具有寄生参数的功率MOSFET建模，用于分析Cdv / dt引起的功率转换器效应
4. An analytical model for evaluating the influence of device parasitics on Cdv/dt induced false turn-on in SiC MOSFETs [C] . Khanna Raghav, Amrhein Andrew, Stanchina William, Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition . 2013

机译：用于评估器件寄生效应对SiC MOSFET中Cdv / dt引起的误导通的影响的分析模型
5. Behavioral Modelling of the Transient and CdV/dt Induced Turn-On of a Hybrid High Power Switch Unit [D] . Macdonald, Jacob Andrew. 2021

机译：混合高功率开关单元的瞬态和CDV / DT诱导开启的行为建模
6. Modeling and Analysis of vgs Characteristics for Upper-Side and Lower-Side Switches at Turn-on Transients for a 1200V/200A Full-SiC Power Module [O] . Maosheng Zhang, Na Ren, Qing Guo, 2020

机译：1200V / 200A全SiC电源模块在开启瞬态时上侧和下侧开关的vgs特性的建模和分析
7. Predicting SiC MOSFET behaviour under hard-switching, soft switching and false turn-on conditions. [O] . Ahmed, Md Rishad, Todd, Rebecca, Forsyth, Andrew 2017

机译：在硬开关，软开关和错误导通条件下预测siC mOsFET的行为。

An analytical model for evaluating the influence of device parasitics on Cdv/dt induced false turn-on in SiC MOSFETs

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