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首页> 外文期刊>IEEE Transactions on Power Electronics >A New Analytical Model for Predicting $dv/ dt$-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters
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A New Analytical Model for Predicting $dv/ dt$-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters

机译：一种新的预测 $ dv / dt $ 诱导的低端MOSFET错误开启降压转换器

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摘要

This paper presents new studies of dv/dt-induced low-side MOSFET false trigger when the high-side MOSFET is turned ON in synchronous buck converters. New analytical expressions are derived and utilized to predict both the magnitude and duration of the false triggering pulse to reveal more physical insight into the phenomenon. In contrast to the existing simple analytical model, the new model takes into account effects of nonlinear time-varying nature of the low-side MOSFET drain-to-source capacitance dv/dt, the low-side MOSFET body-diode reverse-recovery current and common-source inductance during the entire high-side MOSFET turn-ON transition. On the other hand, unlike the high-order complex model, which can only be solved numerically, the proposed analytical model is expressed explicitly by a set of parasitic parameters, and consequently their effects on the low-side MOSFET false trigger can be explored much more easily. The model is mostly suitable for low-voltage applications in which false turn-ON of the low-side MOSFET could happen more often than under high-voltage conditions due to lower MOSFET gate threshold voltage and higher dv/dt. The model is tested on an experimental 12-1.35 V, 8 A synchronous buck converter, and predictions are compared with experimental data with favorable correlation.
机译：本文介绍了在同步降压转换器中打开高侧MOSFET时DV / DT引起的低侧MOSFET虚假触发的新研究。推导出新的分析表达式，以预测假触发脉冲的幅度和持续时间，以揭示对该现象的更具物理洞察力。与现有的简单分析模型相比，新模型考虑了低侧MOSFET漏极 - 源电容DV / DT的非线性时变性质的影响，低侧MOSFET Body-Diode反向恢复电流整个高端MOSFET开启转换过程中的共同源电感。另一方面，与只能在数值解决的高阶复杂模型不同，所提出的分析模型由一组寄生参数明确表示，因此它们对低端MOSFET虚假触发的影响很大更容易。该模型主要适用于低压应用，其中低侧MOSFET的假开启可能比MOSFET栅极阈值电压和更高的DV / DT导致的高压条件更频繁。该模型在实验12-1.35V，8A同步降压转换器上进行测试，并将预测与具有良好相关性的实验数据进行比较。

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